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R2M id:R2M

FPGAã«é–¢ã™ã‚‹R2Mã®ãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯ (53)

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FPGAã‚’å§‹ã‚ã‚‹ã¨ãã®å£ - Ryuz's tech blog
FPGAã‚’ã¯ã˜ã‚ã¦ã¿ãŸã„ ã€ŒFPGAã¨ã„ã†ä½•ã‚„ã‚‰é¢ç™½ã„ã‚‚ã®ãŒã‚ã‚‹ã‚‰ã—ãã¦ã€ä½¿ã†ã¨ã™ã”ã„è¨ˆç®—ã‚„ã„ã‚ã„ã‚ãªãƒ‡ãƒã‚¤ã‚¹åˆ¶å¾¡ãŒã§ãã‚‹ã‚‰ã—ã„ã€‚ã€ ã¨ã€èˆˆå‘³ã‚’æŒã£ã¦é ‚ã‘ã‚‹æ–¹ã¯ãã‚Œãªã‚Šã«ã„ã‚‰ã£ã—ã‚ƒã‚‹ã®ã§ã¯ãªã„ã§ã—ã‚‡ã†ã‹ï¼Ÿ æ—©é€Ÿãªã‚“ã‚‰ã‹ã®HDLãªã‚‹è¨€èªžã‚’å‹‰å¼·ã—ã€ä¾‹ãˆã° System Verilog ã‚’å°‘ã—å‹‰å¼·ã™ã‚Œã°ä¸‹è¨˜ã®ã‚ˆã†ãªãƒ—ãƒã‚°ãƒ©ãƒ ã‚’æ›¸ãã“ã¨ãŒå‡ºæ¥ã¾ã™ã€‚ å…¥åŠ›ãƒãƒ¼ãƒˆ a,b ã‹ã‚‰å…¥ã£ã¦ãã‚‹ãƒ‡ãƒ¼ã‚¿ã‚’ã‚¯ãƒãƒƒã‚¯ã‚µã‚¤ã‚¯ãƒ«æ¯Žã«åŠ ç®—ã—ã¦c ã«å‡ºåŠ›ã™ã‚‹ãƒã‚¸ãƒƒã‚¯ã®ã‚½ãƒ¼ã‚¹ã§ã™ã€‚ module add ( input logic reset, input logic clk, input logic [31:0] a, input logic [31:0] b, output logic [31:0] c ); always_ff @( posedge clk ) begin if ( reset ) begin c <=
R2M 2024/11/30
FPGA
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R2M 2024/04/25
LLM

FPGA
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R2M 2024/04/01
GPU

FPGA
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Nintendo Switchã‹ã‚‰ãƒ‡ã‚¸ã‚¿ãƒ«éŸ³å£°ã‚’ã€Œç›´æŽ¥ã€å–ã‚Šå‡ºã™ã€‚FPGAã§ï¼ - Zopfcode
Switchã¯ã‚¤ãƒ¤ãƒ›ãƒ³å‡ºåŠ›ã®éŸ³ãŒã²ã©ã„ã“ã¨ã§æœ‰åã *1ã€‚ ãƒ–ã‚ºã‚ºã‚ºã‚ºâ€¦â€¦â€¦ãƒãƒãƒãƒãƒâ€¦â€¦ ã¨ç†±é›‘éŸ³ã§ã¯æ˜Žã‚‰ã‹ã«èª¬æ˜Žã§ããªã„å‘¨è¾ºå›žè·¯ã®ãŠæ°—æŒã¡ãŒéŸ³ã¨ãªã£ã¦ä¼ã‚ã£ã¦ãã‚‹ã€‚ ãã“ã§USB DACã‚’ä½¿ã„ãŸã„ã®ã ãŒã€ã©ã†ã‚‚æ‰‹æŒã¡ã ã¨ãƒã‚¤ã‚¨ãƒ³ãƒ‰æ©Ÿã«é™ã£ã¦å‹•ã‹ãªã„*2ã€‚åˆ¥ãªã‚„ã‚Šæ–¹ã§ãƒ‡ã‚¸ã‚¿ãƒ«éŸ³å£°ã‚’å–ã‚Šå‡ºã•ãªã‘ã‚Œã°ã€‚ å–ã‚Šå‡ºã—æ–¹ã¯æ§˜ã€…ã‚ã‚‹ã€‚ ãƒ‰ãƒƒã‚¯ã®HDMIå‡ºåŠ› + S/PDIFã‚¹ãƒ—ãƒªãƒƒã‚¿ãƒ¼ï¼ˆTVãƒ¢ãƒ¼ãƒ‰å¿…é ˆï¼‰ Switchç”¨Bluetoothãƒˆãƒ©ãƒ³ã‚¹ãƒŸãƒƒã‚¿ãƒ¼ï¼ˆã¶ã£ã¡ã‚ƒã‘ã“ã‚ŒãŒä¸€ç•ªã‚ªã‚¹ã‚¹ãƒ¡ï¼‰ SwitchãŒèªè˜ã§ãã‚‹USB DDCã§åŒè»¸ãƒ‡ã‚¸ã‚¿ãƒ«ãªã©ã«ã™ã‚‹ Raspberry Piã®UACã‚¬ã‚¸ã‚§ãƒƒãƒˆ Switchã«ç›´ã«æŽ¥ç¶šã§ããªã„DACã‚’ä½¿ã„ãŸã„å ´åˆã¯ã€DDCå¿…é ˆ*3ã§ã‚´ãƒ†ã‚´ãƒ†ã—ã¦ã—ã¾ã†ã€‚ ã€Œãã‚Œãªã‚‰æœ¬ä½“ã«æµã‚Œã‚‹ãƒ‡ã‚¸ã‚¿ãƒ«ä¿¡å·ï¼ˆI2Sï¼‰ã‚’ç›´æŽ¥å–ã‚Šå‡ºã—ã¦ã€S/PDIFã«å¤‰æ›ã™ã‚‹ã—ã‹ãªã„ã‚ˆãï¼ã€ã¨æ€ã„ã¤ã„ãŸ26ã®å¤œã€‚
R2M 2020/08/14
fpga
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Alveo U50ã§10G Ethernetã‚’è©¦ã—ã¦ã¿ã‚‹ - Fixstars Tech Blog /proc/cpuinfo
XGMIIã®åˆ¶å¾¡ä¿¡å· XGMIIã§ã¯Ethernetã®ãƒ•ãƒ¬ãƒ¼ãƒ ã‚’STARTã‹ã‚‰TERMINATEã§å›²ã¾ã‚ŒãŸåŒºé–“ã§è¡¨ã—ã¾ã™ã€‚ ã¾ãŸã€START ã¯å¿…ãšD[7:0]ã€ã¤ã¾ã‚Š0ç•ªç›®ã®ã‚ªã‚¯ãƒ†ãƒƒãƒˆã«ç¾ã‚Œã‚‹ã“ã¨ãŒè¦å®šã•ã‚Œã¦ã„ã¾ã™ã€‚ãŸã ã—ã€ã“ã‚Œã¯32bit PCSã®å ´åˆã§ã€64bit PCSã®å ´åˆã¯0ç•ªç›®åŠã³4ç•ªç›®ã®ã‚ªã‚¯ãƒ†ãƒƒãƒˆã«STARTãŒç¾ã‚Œã‚‹ã“ã¨ã«æ³¨æ„ãŒå¿…è¦ã§ã™ã€‚ STARTã®å‡ºç¾ä½ç½® Ethernetãƒ•ãƒ¬ãƒ¼ãƒ é€å—ä¿¡ä¸ã«ä½•ã‹ã—ã‚‰ç•°å¸¸ãŒç™ºç”Ÿã—ãŸå ´åˆã¯ã€TERMINATEã§ã¯ãªã ERROR ã§ãƒ•ãƒ¬ãƒ¼ãƒ ã‚’çµ‚äº†ã—ã¾ã™ã€‚ æ£å¸¸ãƒ•ãƒ¬ãƒ¼ãƒ ã¨ç•°å¸¸ãƒ•ãƒ¬ãƒ¼ãƒ ä»¥ä¸Šã‚ˆã‚Šã€XGMIIçµŒç”±ã§Ethernetãƒ•ãƒ¬ãƒ¼ãƒ ã‚’å—ä¿¡ã™ã‚‹ã«ã¯ã€Startã‚’æ¤œå‡ºã—ã¦ã€Terminateã‹ErrorãŒæ¥ã‚‹ã¾ã§é–“ã®ãƒ‡ãƒ¼ã‚¿ã‚’èªã¿å‡ºã—ã¤ã¥ã‘ã‚Œã°ã‚ˆã„ã“ã¨ãŒã‚ã‹ã‚Šã¾ã™ã€‚ãŸã ã—ã€å‰è¿°ã®é€šã‚ŠStartã®ä½ç½®ãŒ0ã‚ªã‚¯ãƒ†ãƒƒãƒˆç›®ã‹4ã‚ªã‚¯ãƒ†ãƒƒãƒˆç›®ã‹å¤‰åŒ–ã™ã‚‹ã®ã§ã€
R2M 2020/05/12
FPGA

NIC

network
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R2M 2020/02/18
fpga
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ã‚ªãƒ¼ãƒ—ãƒ³ã‚½ãƒ¼ã‚¹RISC-Vã‚³ã‚¢HummingBirdã«ã¤ã„ã¦èª¿æŸ»(1. ãƒ€ã‚¦ãƒ³ãƒãƒ¼ãƒ‰ã¨ãƒ“ãƒ«ãƒ‰) - FPGAé–‹ç™ºæ—¥è¨˜
RISC-Vã®å®Ÿè£…ã§ã‚ã‚‹HummingBirdã‚’èª¿æŸ»ã—ã¦ã„ãã“ã¨ã«ã—ãŸã€‚ HummingBirdã®æ¦‚è¦ HummingBirdã¯ä¸å›½ã®å¤§å¦ã§é–‹ç™ºã•ã‚ŒãŸRISC-Vã‚³ã‚¢ã§ã€æ£å¼ã«ã¯E203ã¨ã„ã†åå‰ãŒä»˜ã‘ã‚‰ã‚Œã¦ã„ã‚‹ã€‚GitHubã®ãƒšãƒ¼ã‚¸ã‚’å‚ç…§ã™ã‚‹ã¨ã€ã“ã®HummingBirdã‚’é–‹ç™ºã—ãŸç›®çš„ã¯RISC-Vã®äººæ°—ã‚’å‘ä¸Šã•ã›ã€ä¸å›½ã§ã®IoTè¨è¨ˆã«ãŠã‘ã‚‹RISC-Vã®æ™®åŠã‚’ç›®æŒ‡ã™ãŸã‚ã«é–‹ç™ºã—ãŸã¨æ›¸ã„ã¦ã‚ã‚‹ã€‚ ã„ãã¤ã‹ã®ã‚¢ãƒ¼ã‚ãƒ†ã‚¯ãƒãƒ£ã¨ã®é•ã„ ã“ã‚Œã¯HummingBirdã®è§£èª¬æœ¬(ä¸å›½èªž)ã‹ã‚‰å¼•ç”¨ã—ã¦ã¿ã‚‹ã€‚ ARM Cortex-M0 ARM Cortex-M0+ ARM Cortex-M3 E201 E203 E205 Dhrystone(DMIPS/MHz) 0.84(æ¨™æº–) / 1.21(æœ€é©åŒ–æ™‚) 0.94 / 1.31 1.25 1.171 1.23 1.355 Coremark (Core
R2M 2019/11/01
CPU

FPGA
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IBM Power8ãƒžã‚·ãƒ³ã§Alveo U50ã‚’å‹•ã‹ã™ - Fixstars Tech Blog /proc/cpuinfo
ã“ã®ã¨ãã€VivadoÂ 2019.1ã€€ã§ã¯ãªãÂ VivadoÂ 2019.1.3ã€€ã‚’ä½¿ã£ã¦ã„ã‚‹å ´åˆã€ä»¥ä¸‹ã®ã‚ˆã†ãªã€Œãƒ“ãƒƒãƒˆã‚¹ãƒˆãƒªãƒ¼ãƒ ãŒè¦‹ã¤ã‹ã‚‰ãªã„ã€ã¨ã„ã†ã‚¨ãƒ©ãƒ¼ãŒå‡ºã¦ã‚³ãƒ³ãƒ•ã‚£ã‚°ROMã¸ã®æ›¸ãè¾¼ã¿ã«å¤±æ•—ã—ã¾ã™ã€‚ ERROR: [Labtools 27-2149] File /opt/Xilinx/Vivado/2019.1/data/xicom/cfgmem/bitfile/spi_xcu50_pullup.bit not found. Check file name and file permissions. JTAGçµŒç”±ã§ã‚³ãƒ³ãƒ•ã‚£ã‚°ROMã‚’æ›¸ãè¾¼ã‚€ã¨ãã€ã¾ãšã‚¿ãƒ¼ã‚²ãƒƒãƒˆã®FPGAã«JTAGã‹ã‚‰ã‚³ãƒ³ãƒ•ã‚£ã‚°ROMã¸ã‚¢ã‚¯ã‚»ã‚¹ã™ã‚‹è«–ç†ãŒã‚³ãƒ³ãƒ•ã‚£ã‚°ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã•ã‚Œã¾ã™ã€‚ã“ã®ã¨ãã«æ›¸ãè¾¼ã¾ã‚Œã‚‹ãƒ“ãƒƒãƒˆã‚¹ãƒˆãƒªãƒ¼ãƒ ã¯Â (Vivadoã®ã‚¤ãƒ³ã‚¹ãƒˆãƒ¼ãƒ«ãƒ»ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª)/data/xicon/cfgmem/bitfile
R2M 2019/10/31
FPGA
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A Superscalar Out-of-Order x86 Soft Processor for FPGA | TSpace Repository
Title: A Superscalar Out-of-Order x86 Soft Processor for FPGA Abstract (summary): Although FPGAs continue to grow in capacity, FPGA-based soft processors have grown very little because of the difficulty of achieving higher performance in exchange for area. Superscalar out-of-order processor microarchitectures have been used successfully for hard processors for many years, and promise large perform
R2M 2019/03/11
CPU

fpga

x86
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LUT-Network ï½žæœ¬ç‰©ã®ãƒªã‚¢ãƒ«ã‚¿ã‚¤ãƒ ã‚³ãƒ³ãƒ”ãƒ¥ãƒ¼ãƒ†ã‚£ãƒ³ã‚°ã‚’ç›®æŒ‡ã—ã¦ï½ž
2. è‡ªå·±ç´¹ä»‹ â€¢ åŸºæœ¬çš„ã«ã‚µãƒ³ãƒ‡ãƒ¼ãƒ—ãƒã‚°ãƒ©ãƒžï¼ˆå¹³æ—¥ã¯ã‚µãƒ©ãƒªãƒ¼ãƒžãƒ³ã‚„ã£ã¦ã‚‹ï¼’å…ã®çˆ¶è¦ªï¼‰ â€¢ 1976å¹´ç”Ÿã¾ã‚Œ å…¨å›½è»¢ã€…ã¨ã—ã¤ã¤ã‚‚çµå±€ã€ç¦å²¡å‡ºèº«ï¼†ç¦å²¡åœ¨ä½ â€¢ 1998ï½ž Î¼ITRONä»•æ§˜ Real-Time OS HOS-80 ã‚’ãƒªãƒªãƒ¼ã‚¹ â€¢ ç¾åœ¨ HOS-V4a ã«ã¦å„ç¨®çµ„ã¿è¾¼ã¿CPUã«å¯¾å¿œ (ARM,H8,SH,MIPS,x86,Z80,AM,V850,MicroBlaze, etc.) â€¢ 2008ï½ž FPGAç”¨ã‚½ãƒ•ãƒˆã‚³ã‚¢SoCç’°å¢ƒ Jelly ã‚’ãƒªãƒªãƒ¼ã‚¹(MIPSäº’æ›ã‚³ã‚¢) â€¢ ç¾åœ¨ Zynq ä¸Šã«ã¦ Real-Time GPU ã‚„ LUT-Network ã®å®Ÿé¨“ãªã© å„ç¨® Real-Time ã‚³ã‚¢é–‹ç™ºã®å®Ÿé¨“å ´ã¨åŒ–ã™ â€¢ 2018ï½ž LUT-Networkç”¨ã®ç’°å¢ƒ BinaryBrain ã‚’é–‹ç™ºä¸ â€¢ æœ¬æ—¥ã®ãŠé¡Œ â€¢ é›»è„³ãƒ¡ã‚¬ãƒè¨ˆç”»(ä»–ã«ã‚‚ã„ã‚ã„ã‚ã‚„ã£ã¦ã¾ã™ãŒä»Šã¯ã“ã‚Œ) â€¢ Rea
R2M 2019/02/03
fpga

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golangã¨HDLã§å”èª¿ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã™ã‚‹ - Qiita
åŽ»å¹´ã¨å…¨ãåŒã˜å†…å®¹ã§ã‚ã‚Œã§ã™ãŒã€ä»Šå¹´ã¯golangã§ç’°å¢ƒæ§‹ç¯‰ã—ã¦ã¿ã¾ã—ãŸã€‚ æ¦‚è¦ goã‹ã‚‰exportã•ã‚ŒãŸfunctionã‚’verilogã‹ã‚‰å®Ÿè¡Œ verilogã®Taskã‚’goã‹ã‚‰å®Ÿè¡Œ ç’°å¢ƒ Linuxç’°å¢ƒï¼ˆCentOSï¼‰ Modelsim Intel FPGA Starter Edision 10.5b verilog verilogã¯ã€DPI-Cã‚’ä½¿ã†ã®ã§System Verilogã§ã™ã€‚äº‹å‰ã«ã‚³ãƒ³ãƒ‘ã‚¤ãƒ«ã—ã¦dpiheader.hã‚’åãã‚ˆã†ã«ã—ã¾ã™ã€‚ `timescale 1ns/1ps module top(); import "DPI-C" context task go_test_func(input int,output int); export "DPI-C" task sv_test_task; bit [10:0] m; initial begin go_test_fu
R2M 2018/12/08
go

fpga
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FPGA

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R2M 2017/05/03
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python

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FPGA
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