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ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢æ§‹ç¯‰è¨€èªž Chisel ãŒã‚¢ãƒ„ã„ï¼ˆã‹ã‚‚ã—ã‚Œãªã„ï¼‰ - bonotakeã®æ—¥è¨˜
ã„ããªã‚Šã‚¿ã‚¤ãƒˆãƒ«ã¨é–¢ä¿‚ãªã•ãã†ãªè©±é¡Œã‹ã‚‰ã‚¹ã‚¿ãƒ¼ãƒˆã—ã¾ã™ãŒã€ä»Šé€±1ç•ªã®ãƒˆãƒ”ãƒƒã‚¯ã¯ã€ãªã‚“ã¨è¨€ã£ã¦ã‚‚Edge TPUãŒã‚ªãƒ•ã‚£ã‚·ãƒ£ãƒ«ã«ç™ºå£²ã•ã‚ŒãŸã“ã¨ã§ã—ã‚‡ã†ã€‚ ã—ã‹ã‚‚USBæŽ¥ç¶šã®ã‚¢ã‚¯ã‚»ãƒ©ãƒ¬ãƒ¼ã‚¿ãŒãŸã£ãŸ80ãƒ‰ãƒ«å¼±ã§ã™ã‚ˆã€‚æ—¥æœ¬ã ã¨Mouserã§8800å††ã»ã©ã€‚ ã“ã„ã¤ã‚’ã„ã¡æ—©ãå…¥æ‰‹ã§ããŸIdeinç¤¾å†…ã§ã®ãŠè©¦ã—çµæžœãŒã“ã¡ã‚‰ã€‚ Edge TPU(USBç‰ˆ) Mobilenet v2 1.0 224x224 ImageNet Raspberry Pi 3 Model B v1.2 ã§10msã¡ã‚‡ã£ã¨ã§ã—ãŸ pic.twitter.com/BOfSAgUewJâ€” Koichi Nakamura (@9_ties) 2019å¹´3æœˆ5æ—¥ 10msã£ã¦ã“ã¨ã¯ã‚ã¨6msç¨‹åº¦åˆ¥ã®å‡¦ç†ã«å……ã¦ã¦ã‚‚é«˜ç²¾åº¦ã‚«ãƒ¡ãƒ©ã®ãƒ•ãƒ¬ãƒ¼ãƒ ãƒ¬ãƒ¼ãƒˆ60fpsã«é–“ã«åˆã£ã¡ã‚ƒã†ã£ã¦ã“ã¨ã§ã€ã“ã‚Œã¯ããã£é€Ÿã„ã€‚ åƒ•ã¯åŽ»å¹´å¤ã«Edge TPUãŒã‚¢ãƒŠã‚¦ãƒ³ã‚¹
nfunato 2019/03/08
HDL
ãƒªãƒ³ã‚¯
è«–ç†å›žè·¯ã®é«˜ä½åˆæˆã«ã¤ã„ã¦ - Qiita
Deleted articles cannot be recovered. Draft of this article would be also deleted. Are you sure you want to delete this article? ã¯ã˜ã‚ã« ã“ã®è¨˜äº‹ã§ã¯FPGAç‰ã®è«–ç†å›žè·¯ã®è¨è¨ˆæ‰‹æ³•ã®ä¸€ã¤ã®ã‚«ãƒ†ã‚´ãƒªãƒ¼ã§ã‚ã‚‹ã€Œé«˜ä½åˆæˆã€ã«ã¤ã„ã¦æ¦‚ç•¥ã‚’èª¬æ˜Žã—ãŸã„ã¨æ€ã„ã¾ã™ã€‚ãŸã ã—ã€ç†è€…ã®çŸ¥ã‚‹é™ã‚Šã§ã‚‚é«˜ä½åˆæˆã«ã¤ã„ã¦ã¯ã•ã¾ã–ã¾ãªç«‹å ´ã®äººãŒå„æ™‚ä»£ã®è¦–ç‚¹ã§è‰²ã€…ãªã“ã¨ã‚’èªžã£ã¦ã„ã‚‹ã®ã§ã€ã“ã®è¨˜äº‹ã‚‚ãã‚“ãªä¸ã®ä¸€ã¤ã®è§£é‡ˆã‚’è¿°ã¹ã¦ã‚‹ã ã‘ã¨ã¨ã£ã¦é ‚ãã€ä»–ã®è³‡æ–™ç‰ã‚‚å‚è€ƒã«ã—ã¦èˆˆå‘³ã‚’æŒã£ã¦ã„ãŸã ã‘ã‚‹ã¨å¹¸ã„ã§ã™ã€‚ è«–ç†å›žè·¯è¨è¨ˆã«ã¤ã„ã¦ ã¾ãšWikipediaã®è‹±èªžã®è¨˜äº‹(æ—¥æœ¬èªžç‰ˆã¯ã‚ã‚Šã¾ã›ã‚“ã§ã—ãŸ)ã«ã‚ˆã‚‹ã¨ https://en.wikipedia.org/wiki/High-level_synthesis
nfunato 2018/11/23
fpga

hdl
ãƒªãƒ³ã‚¯
UltraZed å‘ã‘ Debian GNU/Linux (v2017.3ç‰ˆ) ã§ Vivado-HLS ã‚’ä½¿ã£ã¦åˆæˆã—ãŸå›žè·¯ã‚’å‹•ã‹ã™ - Qiita
int negative(volatile int *in, volatile int *out, int size){ #pragma HLS INTERFACE m_axi depth=10 port=out offset=slave #pragma HLS INTERFACE m_axi depth=10 port=in offset=slave #pragma HLS INTERFACE s_axilite port=size #pragma HLS INTERFACE s_axilite port=return int i; for (i = 0; i < size; i++){ out[i] = -in[i]; } return(0); } in ã¨ out ã¯ AXI Master Interface ã‚’çµŒç”±ã—ã¦å¤–éƒ¨ã®ãƒ¡ãƒ¢ãƒªã«ã‚¢ã‚¯ã‚»ã‚¹ã—ã¾ã™ã€‚ã¾ãŸã€ã“ã®å›žè·¯ã®åˆ¶å¾¡ã¯ AXI-L
nfunato 2018/01/08
linux

fpga

hdl
ãƒªãƒ³ã‚¯
SystemVerilog ã‚’ä½¿ç”¨ã—ãŸXilinx FPGAé–‹ç™º
nfunato 2017/10/17
hdl
ãƒªãƒ³ã‚¯
é«˜ä½åˆæˆã‚³ãƒ³ãƒ‘ã‚¤ãƒ©ã‚’ä½œã£ã¦ã¿ãŸã„â‘ - Qiita
ã“ã‚Œã¯è¨€èªžå®Ÿè£… Advent Calendar 2016ã®4æ—¥ç›®ã®è¨˜äº‹ã§ã™ã€‚ ã“ã¡ã‚‰ã¯ä¸€èˆ¬çš„ãªãƒ—ãƒã‚°ãƒ©ãƒŸãƒ³ã‚°è¨€èªžã®å‡¦ç†ç³»ã¨ã¯ç›®çš„ã‚‚ä½œã‚Šæ–¹ã‚‚å…¨ãç•°ãªã‚‹è¨€èªžå‡¦ç†ç³»ã«ã¤ã„ã¦ã€å‹‰å¼·ã—ã¦å®Ÿéš›ã«ä½œã£ã¦ã¿ã‚ˆã†ã¨ã„ã†ä¼ç”»ã¨ãªã‚Šã¾ã™ã€‚ ä»Šå›žã¯å‹•ä½œè¨˜è¿°ã‹ã‚‰ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢è¨˜è¿°è¨€èªžã¸ã¨ã‚³ãƒ³ãƒ‘ã‚¤ãƒ«ã™ã‚‹é«˜ä½åˆæˆã‚³ãƒ³ãƒ‘ã‚¤ãƒ©ãŒãƒ†ãƒ¼ãƒžã§ã™ã€‚å…ƒã€…ã¯ã“ã®ï¼‘å›žã§å˜ç´”ãªã‚³ãƒ³ãƒ‘ã‚¤ãƒ©ã®å®Ÿè£…ã¾ã§ã‚’å®Œçµã•ã›ã‚‹ã¤ã‚‚ã‚Šã§ã—ãŸãŒã€å®Ÿè£…ãŒé–“ã«åˆã„ã¾ã›ã‚“ã§ã—ãŸã®ã§ã€ã‚«ãƒ¬ãƒ³ãƒ€ãƒ¼ã®ç©ºã„ã¦ã„ã‚‹æ—¥ã‚’ã‚‚ã†ï¼‘æ—¥é ‚ã„ã¦ï¼‘æ—¥ç›®ã‚’å‹‰å¼·ç·¨ã€ï¼’æ—¥ç›®ã‚’å®Ÿè£…ç·¨ã¨ã„ã†äº‹ã«ã—ãŸã„ã¨æ€ã„ã¾ã™ã€‚ ä»Šå›žã¯ã€çŸ¥äººã«ç´¹ä»‹ã‚’é ‚ãã¾ã—ãŸä»¥ä¸‹ã®è«–æ–‡ã‚’å‹‰å¼·ã™ã‚‹äº‹ã«ã—ã¾ã—ãŸã€‚çµæ§‹typoã‚„çµ„ç‰ˆå´©ã‚ŒãŒå¤šã„ã®ã§èªã‚€éš›ã¯æ³¨æ„ã—ã¦ãã ã•ã„ã€‚å›žè·¯è¨è¨ˆã®åˆ†é‡Žã¯éžå¸¸ã«åºƒç¯„ãªã®ã§ã‚‚ã¡ã‚ã‚“ã“ã®è«–æ–‡ã®æ‰‹æ³•ãŒå…¨ã¦ã§ã¯ã‚ã‚Šã¾ã›ã‚“ã€‚ Chaiyakul, Viraphol, and Daniel D. Gajski. Ass
nfunato 2016/12/07
compiler

hdl
ãƒªãƒ³ã‚¯
ç¬¬1å›žFPGAã‚¹ã‚¿ãƒ¼ãƒˆã‚¢ãƒƒãƒ—ã‚»ãƒŸãƒŠãƒ¼ã§ã€Œå®Œå…¨ã‚ªãƒ¼ãƒ—ãƒ³ã‚½ãƒ¼ã‚¹HDLåˆæˆã¨Forthãƒžã‚·ãƒ³å®Ÿè£…ã€ã¨ã„ã†LTã‚’ã—ãŸè©±
ç¬¬1å›žFPGAã‚¹ã‚¿ãƒ¼ãƒˆã‚¢ãƒƒãƒ—ã‚»ãƒŸãƒŠãƒ¼ã§ã€FPGAã‚‚Verilogã‚‚ã¾ã£ãŸãã‚ã‹ã‚‰ãªã„ã®ã«LTã—ã¦ã—ã‚ƒã¹ã£ã¦ãã¾ã—ãŸã€‚ãªã‚“ã§ã‚½ãƒ•ãƒˆå±‹ãŒFPGAãƒã‚¿ã§LTã—ãŸã®ã§ã—ã‚‡ã†ï¼Ÿãã“ã«ã¯ç†±ã„æ€ã„ãŒã‚ã‚‹ã‹ã‚‰ã§ã™ï¼ ã¨ã“ã‚ãŒæ®‹å¿µãªã“ã¨ã«æº–å‚™ãŒé–“ã«åˆã‚ãªãã¦ã‚¹ãƒ©ã‚¤ãƒ‰ã‚’ä½œã‚‰ãšã«Webãƒšãƒ¼ã‚¸ã¨å‹•ç”»è¦‹ã‚‹ã ã‘ã§LTã—ã¦ãã¡ã‚ƒã„ã¾ã—ãŸã€‚ã“ã‚Œã ã¨ã‚»ãƒŸãƒŠãƒ¼ã«å‚åŠ ã—ã¦ã„ãªã‹ã£ãŸæ–¹ã«ã¯ã¾ã£ãŸãä¼ã‚ã‚‰ãªã„ã®ã§ã€ã©ã‚“ãªè©±ã‚’ã—ãŸã®ã‹æ›¸ã“ã†ã¨æ€ã„ã¾ã™ã€‚ ã¾ãšã¯ä»¥ä¸‹ã®å‹•ç”»ã‚’è¦‹ã¦ãã ã•ã„ã€‚ è¬ŽæŠ€è¡“ï¼ã—ã‚‡ã¼ã„latticeã®FPGAã§ã‚ã‚‹iCE40ã¨ã„ã†çŸ³ã®ä¸Šã§Forthè¨€èªžãƒžã‚·ãƒ³ãŒå‹•ä½œã—ã¦Linuxã‹ã‚‰ã‚·ãƒªã‚¢ãƒ«ã§ç¹‹ã„ã ä¸Šã§Forthè¨€èªžã®REPLãŒå‹•ã„ã¦ãƒ—ãƒã‚°ãƒ©ãƒŸãƒ³ã‚°ã§ãã¡ã‚ƒã£ã¦ã¾ã™ã€‚ã—ã‹ã‚‚ã‚½ãƒ•ãƒˆã‚¦ã‚§ã‚¢ã«ã‚ˆã‚‹ã‚¤ãƒ³ã‚¿ãƒ¼ãƒ—ãƒªã‚¿ã˜ã‚ƒãªã„è¨¼æ‹ ã«ã€å‹•ç”»ã®æœ€å¾Œã«ã¯ã€ã‚·ãƒªã‚¢ãƒ«ã‚³ãƒ³ã‚½ãƒ¼ãƒ«ã‹ã‚‰æ‰“ã¡è¾¼ã‚“ã ã‚¹ã‚¯ãƒªãƒ—ãƒˆãŒãƒ¡ã‚¬ãƒ˜ãƒ«ãƒ„ã‚ªãƒ¼ãƒ€ãƒ¼ã®ç¶ºéº—ãªçŸ©å½¢æ³¢ã‚’æã‘ã‚‹
nfunato 2016/11/20
forth

hdl
ãƒªãƒ³ã‚¯
HardCaml
The following are executable IOCamlJS notebooks (quick start). Tutorials Basic HardCaml tutorials. Introduction Design Flow Combinatorial Logic Sequential Logic Simulation Guarded DSL Instantiation Examples Prefix networks Linear Feedback Shift Registers Comparison Comparison with other HDLs. Chisel
nfunato 2016/06/13
ocaml

hdl
ãƒªãƒ³ã‚¯
ã‚½ãƒ•ãƒˆã‚¦ã‚§ã‚¢/ã‚¿ã‚¤ãƒŸãƒ³ã‚°ãƒãƒ£ãƒ¼ãƒˆæ¸…æ›¸ã‚µãƒ¼ãƒ“ã‚¹
æ¦‚è¦â€ ã“ã®ã‚ˆã†ãªãƒ†ã‚ã‚¹ãƒˆã‚’å…¥åŠ›ã™ã‚‹ã¨ã€ aclk ~_~_~_~_~_~_~_~_~_~_ awaddr ==?X=A1==X=A2X=A3==X==?=X=A4X=? awvalid __~~~~~~~~~~____~~__ awready ____[~~~~]__[~~]____[~~]__ wdata ====?X=D1X=D2X=?X=D3X=?X=D4==X=? wvalid ____~~~~__~~__~~~~__ wready ____~~~~__~~____~~__ bresp ====00================ bvalid ____~~~~__~~____~~__ bready ~~~~~~~~~~~~~~~~~~1~~ ã“ã‚“ãªã‚¿ã‚¤ãƒŸãƒ³ã‚°ãƒãƒ£ãƒ¼ãƒˆã‚’ç”Ÿæˆã§ãã‚‹ã‚µãƒ¼ãƒ“ã‚¹ã§ã™ã€‚ ã‚½ãƒ¼ã‚¹ã‚³ãƒ¼ãƒ‰ç·¨é›†ä¸ã«ã€ã»ã¼ãƒªã‚¢ãƒ«ã‚¿ã‚¤ãƒ ã§æ¸…æ›¸çµæžœã‚’ç¢ºèªã§ãã‚‹ã®ã§ã€è©¦è¡ŒéŒ¯èª¤ã—ã¦ã„ã‚‹ã†ã¡
nfunato 2016/02/10
hdl
ãƒªãƒ³ã‚¯
iverilog ã¨ verilisp ã‚’ä½¿ã† - Qiita
Icarus Verilog(iverilog) ã‚’ç°¡å˜ã« cygwin ã§ä½¿ãˆã‚‹ã¨èžã„ãŸã®ã§è©¦ã—ã«ä½¿ã£ã¦ã¿ã‚‹ã“ã¨ã«ã—ã¾ã—ãŸã€‚ã¤ã„ã§ã« verilisp ã‚‚ä½¿ã£ã¦ã¿ã¾ã™ã€‚ #ã¾ãšã¯ cygwin(64bit) ä¸Šã§ã‚³ãƒ³ãƒ‘ã‚¤ãƒ« Icarus Verilog ã®ã‚½ãƒ¼ã‚¹ã‚’ github ã‹ã‚‰ clone ã—ã¾ã™ã€‚ $ git clone git://github.com/steveicarus/iverilog.git ã—ã‹ã—ã€configure ãŒã‚ã‚Šã¾ã›ã‚“ã€‚autoconf ã‹ã‚‰å®Ÿè¡Œã—ãªã„ã¨ã„ã‘ãªã„ã‚ˆã†ã§ã™ã€‚ã¨ã„ã†ã“ã¨ã§ã€cygwin ã§ã‚³ãƒ³ãƒ‘ã‚¤ãƒ«ã™ã‚‹ã«ã¯æ¬¡ã®ã‚‚ã®ãŒå¿…è¦ã§ã—ãŸã€‚ autoconf gperf flex bison ã¤ã„ã§ã« clisp ã‚‚ã‚¤ãƒ³ã‚¹ãƒˆãƒ¼ãƒ«ã—ã¦ãŠãã¾ã™(ã‚ã¨ã§ verilisp ã§ä½¿ã†ã‹ã‚‰)ã€‚autoconf ã¯ï¼’ç¨®é¡žã‚ã£ãŸã®ã§ã™ãŒ autoconf-2.69 ãªã‚‹
nfunato 2015/12/14
hdl
ãƒªãƒ³ã‚¯
ZEROã‹ã‚‰ã®FPGA : ç‹¬è‡ªCPUã‚’è‡ªä½œã™ã‚‹ï¼ˆVerilog HDLç‰ˆï¼‰
ã€æ›´æ–°å±¥æ´ã€‘ 2016/12/23 ç°¡æ˜“ã‚¢ã‚»ãƒ³ãƒ–ãƒ©ã‚’æ›´æ–° 2015/12/27 sraã‚’ä¿®æ£ã€ãƒ‡ãƒãƒƒã‚°ç”¨é…ç·šã‚’å‰Šé™¤ 2015/11/02 brã®åå‰ã‚’blã«å¤‰æ›´ã€‚cgtaã‚’è¿½åŠ ã€sr, sl, sra, mv, bcã®ä»•æ§˜ã‚’å¤‰æ›´ 2015/11/01 ç¬¦å·ä»˜ãä¹—ç®—ã«ä¿®æ£ 2015/11/01 æ–°è¦å…¬é–‹ FPGAä¸Šã«ç‹¬è‡ªè¨è¨ˆã®CPUã‚’å®Ÿè£…ã—ã¦ã¿ã¾ã™ã€‚ ã‚¢ãƒ¼ã‚ãƒ†ã‚¯ãƒãƒ£ã¯ã“ã¡ã‚‰ã®ã‚‚ã®ã¨åŒä¸€ã§ã€ãã‚Œã‚’Verilog HDLã§å®Ÿè£…ã—ãŸã‚‚ã®ã§ã™ã€‚ ã‚ˆã‚Šé«˜æ©Ÿèƒ½ã€é«˜é€ŸãªCPUã«æ˜ åƒã€éŸ³å£°å‡ºåŠ›ã€UARTç‰ã‚’å®Ÿè£…ã—ãŸã‚‚ã®ã¯ã“ã¡ã‚‰ã€Œç‹¬è‡ªCPUã‚’è‡ªä½œã™ã‚‹ï¼ˆãƒ¡ãƒ¢ãƒªæ“ä½œã®é€Ÿã„ã‚¢ãƒ¼ã‚ãƒ†ã‚¯ãƒãƒ£ç·¨ï¼‰ã€ã§ã™ã€‚ å°ã•ã„å›žè·¯è¦æ¨¡ã€é«˜ã„å‹•ä½œå‘¨æ³¢æ•°ã‚’ç‹™ã£ãŸCPUã¯ã“ã¡ã‚‰ã€Œå›žè·¯è¦æ¨¡ãŒå°ã•ãé«˜ã‚¯ãƒãƒƒã‚¯ã§å‹•ä½œã™ã‚‹CPUã®è¨è¨ˆã€ã§ã€ãã‚Œã§ãƒ¡ãƒ‹ãƒ¼ã‚³ã‚¢ã‚’æ§‹æˆã—ãŸã‚‚ã®ã¯ã“ã¡ã‚‰ã€Œãƒ¡ãƒ‹ãƒ¼ã‚³ã‚¢ãƒ»ãƒ—ãƒã‚»ãƒƒã‚µãƒ¼ã®è¨è¨ˆã€ã§ã™ã€‚ ã‚¿ãƒ¼ã‚²ãƒƒãƒˆãƒœãƒ¼ãƒ‰ã«ã¤ã„ã¦ ã“ã®
nfunato 2015/11/01
hdl
ãƒªãƒ³ã‚¯
1