A New Transistor Clamped 5-Level H-Bridge

Multilevel Inverter with voltage Boosting Capacity

Prakash Singh, Sachin Tiwari, KK Gupta
Dept. of Electrical & Electronics Engineering Student Member IEEE
Oriental Institute of Science & Technology Maulana Azad National Institute of Technology
Bhopal, India Bhopal, India
[email protected] [email protected]

Abstract — Multilevel converters offer high power capability, (capacitor-clamped) and cascaded H-bridge multilevel
resulting with lower output harmonics and lower commutation inverter. There are also various other topologies which have
losses. Their main disadvantage is their complexity, requiring a been proposed and have successfully adopted in various
great number of power devices and passive components, and a industrial applications. The novel universal multi-carrier
rather complex control circuitry. This paper presents a new PWM control scheme is used .This paper mainly focuses
topology of the multilevel inverter with feature like output
mainly on the cascaded H-bridge inverter topology. The
voltage boosting capability along with capacitor voltage
balancing .The proposed multilevel inverter uses transistor cascaded multilevel inverter has the potential to be the most
clamped H-bridge (TCHB) with an bidirectional switch and reliable out of three topologies. It has the best fault tolerance
four auxillary switches producing a boost output voltage . The owing to its modularity a feature that enables the inverter to
single unit of new topology produces five-level output with continue operate at lower power levels after cells
output voltage double the input DC voltage where as a single failure[2]-[4]. Due to the modularity of the cascaded
unit of conventional H-bridge produces three-level output multilevel inverter it can be stacked easily for high power and
voltage similar to input DC voltage. The comparison has made high voltage applications. The cascaded multilevel inverter
between the proposed five-level inverter and conventional mainly consists of several identical H-bridge cells which are
cascaded five-level inverter in terms of the output voltage , total
cascaded in series from the output side. The cascaded
harmonic distortion (THD) , No. of switching devices used etc.
The analysis of the output voltage harmonics is carried out and H-bridge (CHB) may further be classified as symmetrical if
compared with conventional cascaded H-bridge inverter the DC bus voltage is equal in all the series power cells and as
topology. The proposed multilevel inverter topology is modeled asymmetrical if the DC bus voltage is not same for each
using matlab / simulink. From the results the proposed inverter power cell. The symmetrical CHB is more advantageous over
provides more output voltage. the asymmetrical CHB in terms of modularity, maintenance
and cost. In case of the asymmetrical CHB DC bus voltage is
Keywords— multilevel inverter; cascaded H-bridge; varied in each power as per the requirement to increase the
multicarrier pulse width modulation; transistor clamped inverter, voltage levels [2], [5]. In case of the symmetrical CHB the
cascaded neutral –point clamped inverter
voltage level can be increased without varying the DC
I. INTRODUCTION voltage with same number of power cells. The transistor
clamped topology is popular now a days as it provides
There are various application varying from medium voltage
provision to increase the output levels by taking different
to high voltage high power application which requires DC to
voltage levels from the series stacked capacitors [6], [7]. In
AC conversion using multilevel inverters. The research on
this paper the new configuration of the (symmetrical
multilevel inverter is ongoing further to reduce the number of
H-bridge) single phase 5-level inverter is proposed which
switching devices count to reduce the manufacturing cost,
produces a five-level output voltage instead of three-level as
capacitor voltage balancing. The inverters with number of
in case of conventional H-bridge. Also this new proposed
voltage levels equal to three or above than that are known as
topology produces the boost output voltage in comparison to
the multilevel inverters. Multilevel inverters are capable of
conventional H-bridge topology which requires two H-bridge
producing high power high voltage as the unique structure of
cells producing the five-level output voltage but the output
the multilevel voltage source inverter allows to reach high
voltage equal to the input DC voltage.
voltages with low harmonics without the use of transformers
or series connected synchronized switching devices. As the
number of voltage levels increases, the harmonic content of
II. PROPOSED CONVERTER CONFIGURATION
the output voltage waveform decreases. The synthesized
multilevel outputs are superior in quality which results in The conventional H-bridge inverter consists of DC voltage
reduced filter requirements [1].There are three major for each H-bridge and only four switching devices. The
multilevel voltage source inverter topologies neutral-point value of the DC voltage in each bridge depends whether the
clamped inverter (i.e. diode clamped), flying capacitor configuration is symmetric or unsymmetric.Fig.1 shows the
conventional H-bridge. The general block diagram for the
proposed inverter is shown in fig.2 and the general

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configuration of the proposed inverter topology is shown in
fig.4 which also represents a single cell which produces the
five-level output with boost output voltage. It consist of
total of four main controlled switches and five auxillary
switches including an additional bidirectional switch
consisting of S11 and S11’ in a single cell which is
connected between the first leg of the H-bridge and the
capacitor midpoint, enabling five output voltage levels
(+2Vdc, +Vdc, 0, -Vdc, -2Vdc) based on the switching
combination . The switches S21, S31, S41, S51 forms the
H-bridge and the remaining switches Sa1, Sa2, Sa3, Sa4 are
auxillary switches connected in the same leg which plays a
role in boosting the voltage and the input DC voltage is
connected with positive terminal between the switches Sa1
and Sa2 and the negative terminal between the switches Sa3
and Sa4. The capacitor voltage divider is formed by C1 and
C2.

Fig.4 Conventional H-Bridge based Single-phase 5-level Cascaded

multilevel inverter

Fig.1 Conventional H-bridge

Fig.2 General block diagram of new topology

Fig.4 Proposed Single-phase 5-level multilevel inverter
III. COMPARISON OF DIFFERENT 5-LEVEL switches with the zero value are in the OFF state at the same
INVERTERS instant of time. The look up table for the proposed inverter is
Table.1 COMPARISON OF DIFFERENT 5-LEVEL INERTER given in the figure given below.
TOPOLOGIES
Table.2 SWITCHING PATTERN FOR THE PROPOSED 5-LEVEL
Multilevel Proposed Conventional Diode Capacitor INVERTER
Inverter Inverter H-Bridge Clamped Clamped
No. of
Conducting 8 8 8 8
Voltage +2Vdc +Vdc 0 -Vdc -2Vdc
switches level
No. of
auxillary 1 0 0 0 Sa1 0 0 0 1 0
switches
No. of
Sa2 0 1 0 0 0
Capacitors 2 0 4 10 Sa3 0 0 0 1 0
No. of Sa4 0 1 0 0 0
Diodes 12 8 20 8
S11 0 1 0 1 0
S21 1 0 1 0 0
The new topology for 5-level multilevel inverter also uses S31 0 0 0 0 1
eight conducting switches out of which four switches i.e S21, S41 0 0 1 1 1
S31, S41 and S51 are forming conventional H-Bridge they
are main conducting switches as only these switches can S51 1 1 0 0 0
produce five-level in the output voltage with one
bidirectional switch S11 while remaining four are referred as V. PWM CONTROL SCHEME
auxillary switches. The auxiliary switch voltage and current
ratings are lower than the ones required by the main Multilevel inverter has to synthesize a staircase waveform by
controlled switches. Auxiliary devices (diodes and using the modulation technique to have the controlled output
capacitors): the new configuration reduces the number of voltage [1]. There are variety of modulation techniques
diodes by 60% (eight instead of 20) and the number of available. Basically the control technique can be classified as
capacitors by 50% (two instead of four) when compared with the pulse width modulation which is considered as the most
efficient method. This PWM is further divided into various
the diode clamped configuration. The new configuration
reduces the number of capacitors by 80% (two instead of 10) PWM techniques such as single pulse PWM, space vector
PWM, multiple pulse PWM, phase displacement control [1].
when compared with the capacitor clamped configuration.
Also two separate voltage sources are required for the For this proposed topology we are using the multicarrier
conventional H-bridge based single phase 5-level cascaded based control technique which can be applied to all the
multilevel inverter. topologies of the multilevel inverter. For any given number
of levels in the output voltage the number of carrier to be used
is given as N-1 Where N is the number of levels in the output
IV. OPERATION OF PROPOSED INVERTER
voltage. Fig.5 represents the triangular shape carrier
TOPOLOGY
waveform and the sinusoidal reference signal showing the
The working of the proposed five-level inverter topology is pulse width modulation technique used for the control.
explained telling how the required five level output is Simply a reference signal is taken which is a sinusoidal signal
produced as: of 50Hz frequency and this reference is compared with the
1. Maximum positive output that can be produced is carrier signal which are the triangular wave .The modulation
the double of the input DC voltage i.e 2Vdc which is index we are using in this modulation technique is 0.95.The
produced when S21 is on connecting the load advantage of this scheme is that it offers the charge balance
positive terminal to the load and S51 is on control in the input DC sources and voltage across the
connecting the load negative terminal to the Vdc capacitor are also balanced [11]. Fig.8 shows the voltage
thus the total output voltage is 2Vdc. The output across the two capacitors` which are equal in magnitude.
voltage level Vdc is obtained when Sa1, S11, S51
and Sa2 gets turned on other switches remaining off.

2. Maximum negative output is -2Vdc which is

produced when switches S41 and S31 gets turned on
connecting the negative and positive terminal of the
load respectively to the input source. The negative
level –Vdc is obtained when switches Sa1, Sa3, S11,
S41 are turned on other switches remaining off.

The detailed operation of the proposed topology can also be

understand through the look up table which is given in Table
2.In the look up table 0 and 1 values are assigned to the
switches for a particular voltage level. At any level of the
output voltage the switches which are having value 1 means
Fig.5 Multicarrier based PWM control scheme
they are in the ON state at that time and the remaining
Fig.6 output voltage waveform of the single-phase 5-level cascaded Fig.8 waveform of the voltage across the capacitors C1 & C2
H-bridge inverter using PWM

VI. COMPARISON OF PROPOSED MULTILEVEL

INVERTER WITH CONVENTIONAL H-BRIDGE
TOPOLOGY
The purpose of research for the multilevel inverter includes to
get a quality power output with the reduced number of
switching devices, balancing of the capacitors, reduced
number of clamping diodes in order to reduce the overall cost
of the multilevel inverter. In the proposed 5-level multilevel
inverter topology the number of switches is only one more
then the 5-level single phase cascaded H-bridge inverter. But
the input DC voltage source required is half of the voltage
source required in the conventional CHB. To produce the
same output voltage the cascaded H-bridge has to use the two
cells where as only one cell is required with the proposed
topology. Fig.4 is showing the proposed single phase 5-level
inverter which also represents a single power cell having
input 150V DC voltage and the output ac voltage is 300V.
The total harmonic distortion produced by the proposed
inverter is 38.11% only, Fig.11 shows the THD in % for
single phase 5-level proposed multilevel inverter which is
very low as compared to the single unit of conventional
H-bridge inverter having THD of 70.99% , Fig.9 shows the
THD in % for single cell of conventional H-bridge multilevel
inverter which is 32.88% more than the proposed topology. If
Fig.7 output voltage waveform of the proposed Single-phase 5-level inverter it is compared with conventional H-bridge based single phase
using PWM 5-level cascaded multilevel inverter which is having THD of
37.80% the THD of proposed 5-level topology is 0.31%
more, Fig.10 shows the THD in % for conventional H-bridge
based single phase 5-level cascaded multilevel inverter. In
order to produce the nine levels in the output voltage the
conventional H-bridge requires three cells where as the
proposed topology requires only two cells.
VII. CONCLUSION
The proposed single phase 5-level multilevel inverter
topology is much superior than the conventional 5-level
single phase cascaded H-bridge topology in terms of the
number of level in the output voltage, magnitude of the
output voltage, total harmonic distortion (THD). Though the
proposed topology uses some extra auxillary switching
devices but they are of smaller ratings and also two capacitors
in comparison to conventional H-Bridge based Cascaded
5-level Multilevel Inverter used. But the greatest advantage
of proposed topology is that the input DC voltage magnitude
required is half of that required in conventional H-Bridge
cascaded H-bridge 5-level single phase topology. The THD
of the proposed topology is also less than the cascaded
H-bridge inverter topology. In comparison with diode
clamped and the flying capacitor type inverter of the same
number of level there is a great reduction in the main power
switching devices, diodes and the capacitors used.
Fig.9 THD in % for single H-bridge multilevel inverter
VIII. REFERENCES:

[1] Rashid, M.H, 2004. “Power Electronics: Circuits, devices

and applications. Third Edition, Prentice Hall.

[2] S.Mukherjee and G. Poddar, "A Series-Connected Three-Level

Inverter Topology for Medium-Voltage Squirrel-Cage Motor Drive
Applications," IEEE Trans. Ind. Appl., vol. 46, pp. 179-186, 2010.

[3] S.Khomfoi and L. M. Tolbert, "Fault Diagnosis and Reconfiguration for

Multilevel Inverter Drive Using AI-Based Techniques," IEEE Trans.Ind.
Electron., vol. 54, pp. 2954-2968, 2007.

[4] P. Lezana and G. Ortiz, "Extended Operation of Cascade

Multicell Converters Under Fault Condition," Industrial Electronics, IEEE
Trans.Ind. Electron., vol. 56, pp. 2697-2703, 2009.

[5] J. Rodríguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey

of topologies, controls, and applications,” IEEE Transaction on
Industrial electronics, vol. 49, no. 4, pp. 724–738, Aug. 2002

[6] Ebrahim Babaei, 2008, “A Cascade Multilevel Converter Topology

With Reduced Number of Switches” IEEE Transactions on power
electronics, Vol. 23, No.6.

Fig.10 THD in % for single phase 5-level cascaded H-bridge multilevel [7] L. M. Tolbert, F. Z. Peng, T. G. Habetler, “Multilevel PWM methods
inverter at low modulation indices,” IEEE Transactions on power electronics, vol. 15,
no. 4, July 2000, pp. 719-725

[8] M. A. Perez, P. Cortes, and J. Rodriguez, "Predictive Control

Algorithm Technique for Multilevel Asymmetric Cascaded H-Bridge
Inverters, "IEEE Trans. Ind. Electron., vol. 55, pp. 4354-4361, 2008.

[9] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo,

B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, "Recent Advances
and Industrial Applications of Multilevel Converters," IEEE Trans.
Ind.Electron., vol. 57, pp. 2553-2580, 2010.

[10] Nasrudin Abd. Rahim, Mohamad Fathi Mohamad Elias, Wooi Ping
Hew, “Transistor-Clamped H-Bridge Based Cascaded Multilevel Inverter
with New Method of Capacitor Voltage Balancing” August 2, 2011; revised
November 22, 2011 and February 27, 2012. Accepted for publication April 8,
2012.

[11] Gupta, Krishna Kumar; Jain, Shailendra; , "A novel universal control
scheme for multilevel inverters," Power Electronics, Machines and Drives
(PEMD 2012), 6th IET International Conference on , vol., no., pp.1-6, 27-29
March 2012

[12] Gerardo Ceglia, Víctor Guzmán, Carlos Sánchez, Fernando Ibáñez,

Julio Walter, and María I. Giménez “A New Simplified Multilevel Inverter
Topology for DC–AC Conversion” IEEE Transactions on Power Electronics,
Vol. 21, No. 5, September 2006.

Fig.11 THD in % for single phase 5-level proposed multilevel inverter