Received November 3, 2018, accepted December 2, 2018, date of publication February 26, 2019, date of current version March

7, 2019.
Digital Object Identifier 10.1109/ACCESS.2019.2890872

Optimal Design of a New Cascaded Multilevel

Inverter Topology With Reduced Switch Count
MARIF DAULA SIDDIQUE 1 , (Student Member, IEEE),
SAAD MEKHILEF 1,2 , (Senior Member, IEEE), NORAISYAH MOHAMED SHAH1 ,
AND MUDASIR AHMED MEMON1
1 Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia
2 Center of Research Excellence in Renewable Energy and Power Systems, King Abdulaziz University, Jeddah 21589, Saudi Arabia
Corresponding author: Saad Mekhilef ([email protected])
This work was supported in part by the University of Malaya, Malaysia, through FRGS under Grant FRGS/1/2018/TK07/UM/01/3, in part
by Frontier Research under Grant FG007-17AFR, in part by BKP under Grant BK052-2016, and in part by Postgraduate Research (PPP)
under Grant PG192-2015B.

ABSTRACT Multilevel inverters (MLIs) are a great development for industrial and renewable energy
applications due to their dominance over conventional two-level inverter with respect to size, rating of
switches, filter requirement, and efficiency. A new single-phase cascaded MLI topology is suggested in
this paper. The proposed MLI topology is designed with the aim of reducing the number of switches and the
number of dc voltage sources with modularity while having a higher number of levels at the output. For the
determination of the magnitude of dc voltage sources and a number of levels in the cascade connection, three
different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher
number of levels while minimizing other parameters. A detailed comparison is made with other comparable
MLI topologies to prove the superiority of the proposed structure. A selective harmonic elimination pulse
width modulation technique is used to produce the pulses for the switches to achieve high-quality voltage at
the output. Finally, the experimental results are provided for the basic unit with 11 levels and for cascading
of two such units to achieve 71 levels at the output.

INDEX TERMS Basic unit, cascaded inverter, multilevel inverter (MLI), selective harmonic elimination,
SHEPWM, optimization, reduce switch count.

I. INTRODUCTION MLI, T-type MLI and modular multilevel converters (MMC).

Multilevel inverters are among the most used power con- These MLI topologies have found their applications with
version devices in industrial applications. These applica- different power and voltage ratings, along with their unique
tions mostly comprise of the motor drives for the entire benefits as well as shortcomings. These shortcomings include
voltage and power ratings. Multilevel inverters (MLIs) are the higher number of components for a higher number of lev-
also finding their applications in the grid-connected systems, els along with capacitor voltage balancing problems. In order
uninterruptible power supply (UPS), electric vehicles and to overcome these drawbacks, several new topologies for the
FACTS devices. All these applications are possible due to multilevel inverter and their control have been introduced
the ability of the MLI to provide a better output voltage with in [8]–[10].
a more sinusoidal shaped waveform, improved efficiency The main driving force for the design of new multilevel
due to the lower switching frequency operation of switches, inverter topologies has been the reduction of the number of
lower blocking voltage requirement with reduced dv/dt and switches, number of dc voltage sources, and total standing
improved electromagnetic compatibility. Another positive voltage (TSV) of the topology. Based on these constraints,
impact of MLI is the reduction of the filter size and cost due several topologies with reduced switch count have been pro-
to the reduced amount of harmonics at the output [1]–[7]. posed in the literature, such as in [11]–[14]. All of them
The conventional multilevel inverter topologies for the have used H-bridge in order to generate the positive and
industrial application include neutral point clamped (NPC) negative polarities of the output voltage waveform. However,
MLI, flying capacitor (FC) MLI, cascade H-bridge (CHB) the switches of H-bridge need to block maximum/peak output

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M. D. Siddique et al.: Optimal Design of a New Cascaded MLI Topology With Reduced Switch Count

voltage, which limits their applications in high voltage. This

problem has been solved in E-type [15] and ST-type [16]
where the topologies inherently generate both positive and
negative levels without using H-bridge. E-type and ST-type
topologies use four dc voltage sources to generate 13 and
17 levels at the output by means of 10 and 12 power semi-
conductor switches respectively. An improved topology has
been presented in [17] which generates 25 levels with four dc
voltage sources. The main problem with [17] is the use of the
diodes, which reduces efficiency.
Several cascaded MLI topologies have been proposed in
[18]–[28] based on the basic units. A basic unit developed FIGURE 1. Basic unit of the proposed topology.
with the H-bridge has been proposed in [18]. It consists of two
dc voltage source with six switches to generate seven levels TABLE 1. Switching table of the proposed basic unit.
at the output. A similar topology has been proposed in [19] in
which both dc voltage sources in [18] has been replaced by the
T-type module having two dc voltage sources and one bidi-
rectional switch. This modification results in 17 levels at the
output. In [20], both topologies presented in [18] and [19] has
been combined and an improved sub multilevel converter has
been proposed. Another topology based on [18] has been pro-
posed in [21] with a reduced number of switches. The basic
unit of [21] produces 17 levels with four dc voltage sources
and 12 switches. The topologies presented in [18]–[25] can
be connected in cascade to achieve a higher number of levels
at the output.
The optimal design of cascaded MLI has been another
important aspect. The optimal selection of number of
cascaded units has been presented in several topolo-
gies [19]–[21]. These optimizations of the topology deal with
the optimal selection of number of cascaded modules such
that higher number of levels are achieved at the output while along with six unidirectional switches and one bidirectional
minimizing the number of switches, driver circuits and dc switch. Switch pair (S1 , S2 ) and (S5 , S6 ) can be termed as
voltage sources. In this paper, an optimal design cascaded outer switches, and only one switch is necessary to be turned
multilevel inverter topology is proposed, which is able to ON from each pair. The switches of outer pairs should also
generate a higher number of levels with reduced number of operate in a complementary mode to avoid short-circuiting
switches. An additional factor has been the variety of dc the dc voltage sources. These outer switches are connected
voltage sources which is reduced in the proposed topology. across voltage source V1 . The remaining two dc voltage
The paper is organized as follows: the analysis and descrip- sources with V2 magnitude are connected in series with
tion of the proposed basic unit with its generalized structure additive polarity, along with unidirectional switches S3 , S4
is presented in Section II. The analysis covers the magnitude and bidirectional switch S11 forms the inner portion of the
selection of dc voltage sources along with total standing proposed basic unit. Only one switch is required to be turned
voltage (TSV) calculations. Section III elaborates the cascade ON in between these three switches. Considering these facts,
connection of the proposed topology, and optimization of the the switching table for the proposed basic unit is given
cascade connection is given in Section IV. Section V provides in Table 1.
a detailed comparison of the proposed topology with existing
ones. Section VI deals with the selective harmonic elimi- B. GENERALIZED STRUCTURE OF PROPOSED TOPOLOGY
nation modulation technique. Simulation and experimental The proposed basic unit is able to achieve 11 levels at the
results are provided in Section VII followed by the conclusion output employing three dc voltage sources. In order to gen-
in Section VIII. erate more number of levels, the basic unit can be extended
as shown in Fig. 2. In this extension, the number of dc
II. ANALYSIS AND DESCRIPTION OF PROPOSED voltage sources, which is connected to the inner portion of the
MULTILEVEL TOPOLOGY module, is increased along with bidirectional switches. The
A. BASIC UNIT OF PROPOSED TOPOLOGY switches used in the proposed topology can be grouped into
Fig. 1 shows the basic unit of the suggested multilevel inverter three cells. Cell 1 is made up of switches S1 and S2 . Switches
topology. The assembly consists of three dc voltage sources in cell 1 are operated at fundamental frequency as both have

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V1 is depend on k. Therefore, with a higher number of dc

voltage sources, the magnitude selection of dc voltage sources
in MODE II becomes impractical. Fig. 3 shows all the voltage
states in a positive half cycle of the basic unit with voltage
sources configured in MODE I.

D. CALCULATION OF TSV
The voltage stress across each switch plays a significant role
in determining the cost and efficiency of an MLI. For this
purpose, total standing voltage (TSV) is considered as a key
parameter [16]. TSV is defined as the sum of maximum
voltage stress across each switch considering each level at the
output. For the proposed topology, TSV can be expressed as:
FIGURE 2. Generalized structure of the proposed topology.
TSV = TSV Cell1 + TSV Cell2 + TSV Cell3 (9)
where TSV Cell1 , TSV Cell2 , and TSV Cell3 are the TSV of cell
to bear maximum voltage stress. Cell 2 consist of all the inner
1, 2, and 3 respectively. All these values are given as
switches and each switch turns ON for any two levels in the
one-half cycle. Similarly, cell 3 consist of two switches S5 TSV Cell1 = 2 [V1 + (k − 1) V2 ] (10)
and S6 and both of them operate at a high frequency. TSV Cell2 = M × V2 (11)
The generalized equations for the proposed topology with
k number of dc voltage sources are given as: The value of M can be calculated as follows:
3k 2 − 2k − 1

Maximum number of Levels = N = 4k − 1 (1) M= for odd number of k 

4 (12)
Number of Switches = Nswitch = 2k + 2 (2) 2
3k − 2k 
M= for even number of k 
Number of Driver Circuits = Ndriver = k + 4 (3) 4
Peak Output Voltage = Vo,max = V1 + (k − 1) V2 (4) Similarly, for cell 3
Variety of dc sources = Nvariety = 2 (5) TSV Cell3 = 2V1 (13)

C. SELECTION OF MAGNITUDE OF DC VOLTAGE SOURCES Therefore, from (9) – (13)

The selection of dc voltage sources used in the proposed TSV = 4V1 + (M + 2k − 2) V2 (14)
topology is an important criterion for practical applications.
One such benchmark is the variety of dc voltage sources i.e. III. CASCADE CONNECTION OF PROPOSED TOPOLOGY
how many different magnitudes of dc voltage sources are Cascading several modules is another way to increase the
employed in the topology. For the proposed topology, only number of levels at the output. Fig. 4 shows the cascade
two different magnitudes of dc voltage sources are required. connection of the proposed topology with m modules. The
Another important aspect related to dc voltage sources is their output voltage across the load is the sum of all the voltages
magnitude selection. For the proposed topology, the peak generated by each module connected in cascade, i.e.,
output voltage of the proposed topology is given in (6).
Vo = Vo1 + Vo2 + . . . + Vom (15)
N −1
Vo,max = V1 + (k − 1) V2 = × Vdc (6) In order to maintain the modulatory, each module con-
2
nected in cascade is assumed to be identical i.e. each module
For the generalized structure, the selection of dc voltage has the same number of switches and dc voltage sources.
sources can be done in two modes. In MODE I, the magnitude The equations for the proposed topology with m modules in
of V1 is selected as Vdc . Then from (1) and (6), the magnitude cascade, and with k number of dc voltage sources in each
of V2 is calculated as module are given as:
V2 = 2Vdc (7) Nswitch = m × (2k + 2) (16)
Similarly, in MODE II, the magnitude of V2 is fixed as Vdc . Ndriver = m × (k + 4) (17)
Then the magnitude of V1 from (1) and (6) is Nsource = m × k (18)
N − 2k + 1 The number of output levels for the cascade connection
V1 = V = kV dc (8)
2 dc depends on the magnitude of dc voltage sources in each
The magnitude of dc voltage sources in MODE I is fixed module. The magnitude of dc voltage sources of each module
as V1 = Vdc and V2 = 2Vdc irrespective of the number of can be selected by three different algorithms, described as
dc voltage sources, whereas for MODE II, the magnitude of follows.

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FIGURE 3. Different switching states of the proposed basic unit with MODE I in positive half cycle.

In MODE I,
V11 = V21 = Vm1 = Vdc (19)
V12 = V22 = Vm2 = 2V dc (20)
In MODE II,
V11 = V12 = Vm1 = kV dc (21)
V21 = V22 = Vm2 = Vdc (22)
In both modes, the number of levels from the first algorithm
Nlevel,F at the output is given by:
Nlevel,F = [{m × (4k − 2)} + 1] (23)
Variety of dc sources = Nvariety = 2 (24)

B. SECOND ALGORITHM (SA)

In this algorithm, the magnitude of the first module is the
same as that of the first algorithm, but for other modules,
the selection is made according to the following equations
for both modes.
For the 1st module:
In MODE I,
V11 = Vdc (25)
V12 = 2V dc (26)
In MODE II,
V11 = kVdc (27)
FIGURE 4. Cascade connection of proposed MLI.
V12 = Vdc (28)
The maximum/peak output voltage of the 1st module is given
A. FIRST ALGORITHM (FA) by:
In this algorithm, the magnitude of dc voltage sources associ- Vo1,max = V11 + (k − 1) V12 (29)
ated with the individual module is the same. The magnitude
selection can be done based on either MODE I or MODE II. For the 2nd module:

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In MODE I, The maximum/peak output voltage of the 1st module is given

by:
V21 = (Vo1,max + Vdc ) (30)
Vo1,max = V11 + (k − 1) V12 (46)
V22 = 2 × (Vo1,max + Vdc ) (31)
For the 2nd module:
In MODE II, In MODE I,
V21 = k × (Vo1,max + Vdc ) (32) V21 = (2Vo1,max + Vdc ) (47)
V22 = (Vo1,max + Vdc ) (33) V22 = 2 × (2Vo1,max + Vdc ) (48)
The maximum/peak output voltage of the 2nd module is given In MODE II,
by: V21 = k × (2Vo1,max + Vdc ) (49)
Vo2,max = V21 +(k − 1) V22 = (2k − 1) × (V o1,max + Vdc ) V22 = (2Vo1,max + Vdc ) (50)
(34) The maximum/peak output voltage of the 2nd module is given
by:
Similarly, for the mth module:
In MODE I, Vo2,max = V21 +(k − 1) V22 = (2k − 1)×(2V o1,max + Vdc )
(51)
Vm1 = (Vo(m−1),max + Vo(m−2),max + Vdc ) (35)
Vm2 = 2 × (V o(m−1),max + Vo(m−2),max + Vdc ) (36) Similarly, for the mth module:
In MODE I,
In MODE II, Vm1 = (2V o1,max + 2Vo2,max + . . . + 2Vo(m−1),max + Vdc )
Vm1 = k × (Vo(m−1),max + Vo(m−2),max + Vdc ) (37) (52)
Vm2 = (Vo(m−1),max + Vo(m−2),max + Vdc ) (38) Vm2 = 2 × (2V o1,max +2Vo2,max +. . .+2Vo(m−1),max +Vdc )
(53)
The maximum/peak output voltage of the mth module is given
by: In MODE II,

Vom,max = (2k − 1) × (V o(m−1),max + Vo(m−2),max + Vdc ) Vm1 = k × (2V o1,max +2Vo2,max +. . .+2Vo(m−1),max + Vdc )
(39) (54)
Vm2 = (2V o1,max +2Vo2,max +. . .+2Vo(m−1),max +Vdc )
where Vo(m−1),max and Vo(m−2),max represent the peak output
(55)
voltage of (m-1)th and (m-2)th modules connected in cascade,
respectively. In both modes, the number of levels from the The maximum/peak output voltage of the mth module is given
second algorithm Nlevel,S at the output is given by by:
2 Vo1,max + Vo2,max + . . . + Vom,max Vom,max = (2k − 1)×(2V o1,max +. . .+2Vo(m−1),max +Vdc )

Nlevel,S = +1
Vdc (56)
Nlevel,S = 2 × (2k)m − 1 (40) where Vo(m−1),max represents the peak output voltage of (m-
Variety of dc sources = Nvariety = 2m (41) 1)th module connected in cascade. In both mode of operation,
the number of levels with the third algorithm Nlevel,T at the
C. THIRD ALGORITHM (TA) output is given by:
In this algorithm, the magnitude of the first module is same
Nlevel,T = (4k − 1)m (57)
as that of the first algorithm but for other modules, the selec-
tion is decided according to the following equations in both Variety of dc sources = Nvariety = 2m (58)
modes.
For the 1st module: IV. OPTIMIZATION OF THE PROPOSED TOPOLOGY IN
In MODE I, CASCADE CONNECTION
The optimization analysis of the proposed cascaded MLI in
V11 = Vdc (42) all three algorithms is presented in this section. The opti-
V12 = 2V dc (43) mization of a topology is helpful to minimize the number of
switches, number of driver circuit and number of dc voltage
In MODE II, sources required in order to generate a higher number of
levels at the output. Five different aspects of optimization
V11 = kVdc (44) is considered for the proposed topology and are discussed
V12 = Vdc (45) below.

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FIGURE 5. Curves related to optimization for (a) constant number of FIGURE 6. Curves related to optimization for (a) minimization of switches
switches and (b) constant number of dc voltage sources for maximum and (b) minimization of driver circuit with constant number of levels.
number of level generation.

cascade MLI generates a maximum number of levels for all

A. OPTIMIZATION OF THE PROPOSED MLI WITH A three algorithms. From (20):
CONSTANT NUMBER OF SWITCHES FOR A MAXIMUM Nsources
NUMBER OF LEVELS m= (63)
k
In this section, the number of switches is made constant and From (25), (42), (59), and (63),
the number of the dc voltage source in each module is varied
4k − 2
in order to generate the maximum number of levels at the Nlevel,F = Nsources × +1 (64)
output. From (16): k
Nsources

Nswitches Nlevel,S = 2 × (2k) k

−1 (65)
m= (59)
Nsources

(2k + 2) Nlevel,T = (4k − 1) k
(66)
From (23), (40), (57), and (59), Fig. 5 (b) shows the variation of the number of levels with k
4k − 2 and constant Nsources . The number of levels is maximized
as
Nlevel,F = NSwitches × +1 (60) 1
2k + 2 4k−2 k
the termsassociated with (64)-(66) i.e. k , 2×(2k) , and
NSwitch
1
Nlevel,S = 2 × (2k) 2k+2
−1 (61) (4k − 1) k
attain their maximum value. For FA, the topol-

NSwitch
ogy is optimized with k = ∞. Similarly, from Fig. 5 (b),
Nlevel,T = (4k − 1) 2k+2
(62)
the proposed structure is optimized in the second and third
As NSwitches is constant 4k−2
in (60)-(62), the terms 2k+2 , algorithm with k = 2.

1 1
(2k) 2k+2 , and (4k − 1) 2k+2 should be maximum in order C. MINIMIZING THE NUMBER OF SWITCHES WITH
to achieve more number of levels at the output with the CONSTANT NUMBER OF LEVELS
optimized structure of the proposed topology. Fig. 5 (a) shows In this section, the topology is optimized with a constant
the variation of all these terms with respect to the number of number of levels and a minimum number of switches. Using
dc voltage sources k. As indicated by Fig. 5 (a), the proposed (60)-(62) the equations for the number of switches with a
topology is optimized with k = ∞ for the first algorithm, constant number of levels for the three algorithms are given
with k = 2 for the second algorithm and with k = 3 for the as:
third algorithm. 2k + 2
Nswitches,F = (N level,F − 1) × (67)
B. OPTIMIZATION OF PROPOSED MLI WITH A CONSTANT 4k − 2
Nlevel,S + 1 2k + 2
NUMBER OF DC VOLTAGE SOURCES FOR A MAXIMUM Nswitches,S = ln × (68)
NUMBER OF LEVELS
2 ln (2k)
2k + 2
In this optimization, the number of dc voltage sources is Nswitches,T = ln Nlevel,T × (69)
made constant and the variation of k is observed in order to ln (4k − 1)
generate the maximum number of levels at the output. This From (67)-(69), the number of switches is minimized as
optimization decides the value of k for which the proposed the terms 4k−2 , ln(2k) , and ln(4k−1)
2k+2 2k+2 2k+2
are minimized while the

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TABLE 2. Comparison of different basic units for cascade connection.

FIGURE 7. Curves related to optimization for minimization of dc voltage

sources with constant number of levels.

number of levels are kept constant. Fig. 6 (a) displays the

variation of these terms for different algorithms with respect V. COMPARATIVE STUDY
to k. For FA, k = ∞ optimizes the proposed topology, while In order to prove the dominance of the proposed basic unit, a
k = 2 is optimum for both SA and TA algorithm. comparison is made with other similar basic units and is pro-
vided in Table 2. The comparisons are carried out with respect
D. MINIMIZING THE NUMBER OF DRIVER CIRCUIT WITH to the number of switches, number of the driver circuit, num-
CONSTANT NUMBER OF LEVELS ber of dc voltage sources, number of levels generated across
The optimization of the proposed structure is considered by the load and TSV. One important aspect of cascade MLI is
minimizing the number of driver circuits required with a that the basic unit must have a lower number of switches and
constant number of levels. (70)-(72) gives the number of sources. From Table 2, it is clear that the proposed basic unit
driver circuit required with a constant number of levels. uses a lower number of switches except [18]. Furthermore,
the TSV/Nlevels is lower compared to other basic units in both
k +4 modes except [18].
Ndriver,F = (N level,F − 1) × (70)
4k − 2 The main intention of proposing the new cascade topology
Nlevel,S + 1 k +4 is to reduce the number of switches and dc voltage sources
Ndriver,S = ln × (71)
2 ln (2k) while achieving more number of levels at the output. In order
k +4 to benchmark the effectiveness of the proposed topology,
Ndriver,T = ln Nlevel,T × (72)
ln (4k − 1) a comparative study with other comparable MLI topologies
is presented in this section. The comparisons are based on
k+4 k+4 k+4
From these equations, the terms 4k−2 , ln(2k) , and ln(4k−1) the number of switches, number of driver circuit required,
should be minimized in order to get the optimized structure. number of dc voltage sources, and the total standing voltage
The variation of the number of driver circuit against k with against the number of levels. In this comparison, the optimal
a constant number of levels is illustrated in Fig. 6 (b). With design is considered for all topologies including the proposed
respect to the Fig. 6 (b), the optimal number of driver circuit structure. In [19]–[22], two algorithms have been proposed
required for FA is obtained for k = ∞. Similarly, for SA and with an optimal design. The best algorithm of all topologies
TA, the proposed topology optimizes with k = 4 and k = 3 is used for the comparison.
respectively. Fig. 8 (a) shows the variation of number of switches against
the number of levels at the output. It is clear from the Fig. 8 (a)
E. MINIMIZING THE NUMBER OF DC VOLTAGE SOURCES that the proposed topology uses less number of switches com-
WITH CONSTANT NUMBER OF LEVELS pare to other topologies, thus one of the main objectives of
Rewriting (65)-(67), the equations relating the number of dc the newly proposed topology have been achieved. Topologies
voltage sources with respect to k for a constant number of suggested in [19]–[22] and the proposed topology uses bidi-
levels are given in (74)-(77). rectional switches along with unidirectional switches. The
use of bidirectional switches reduces the number of driver
k
Nsource,F = (N level,F − 1) × (73) circuit required if they are configured in common emitter
4k − 2 connection. The variation of the number of driver circuit with
Nlevel,S + 1 k the number of levels is indicated in Fig. 8 (b). The proposed
Nsource,S = ln × (74)
2 ln (2k) topology requires a lower number of driver circuit than other
k topologies except [19], [20].
Nsource,T = ln Nlevel,T × (75)
ln (4k − 1) Reducing the number of dc voltage source has been another
important criterion in the selection of an MLI. Fig. 9 (a)
k k k
The variation of 4k−2 , ln(2k) , and ln(4k−1) is shown in compares the number of dc voltage sources required with
Fig 7. For FA, SA and TA, the topology gets opti- the number of output levels. The proposed topology requires
mized with k = ∞, k = 2, and k = 2 a lower number of dc voltage sources than other topologies
repectively. except [22] and [26]. Another crucial feature of an MLI is the

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FIGURE 8. Variation of (a) number of switches and (b) number of driver FIGURE 9. Variation of (a) number of dc voltage sources and (b) TSV
circuit against number of levels. against number of levels.

lower TSV. Fig. 9 (b) displays the comparison of TSV with

the number of levels achieved at the output. The proposed
topology has the lowest amount of TSV compare to other
MLI structures. Therefore, these comparisons demonstrate
the relevance of the proposed cascaded topology in terms of
achieving higher number of level generation with a reduction
in other parameters.

VI. MODULATION TECHNIQUE FIGURE 10. 11 level staircase output voltage waveform.
The PWM technique used for the gate pulse generation has
been classified into two categories based on the switching
frequency namely high switching frequency PWM and fun- harmonics attain zero value. Therefore, the equation for out-
damental switching frequency PWM techniques. Sinusoidal put voltage modifies to:
PWM, space vector PWM and hybrid modulation PWM are Xn
some of the examples of high switching frequency tech- vo (t) = bn sin (nαi ) (77)
i=1,3,5,...
niques. In these PWM techniques, the number of turn ON For a staircase output voltage, bn can be expressed as:
and turn OFF are high. This results in higher switching losses
which reduce the efficiency [9], [30], [31]. 4Vdc Xn
bn = cos (nαi ) (78)
Fundamental switching frequency is preferred for multi- nπ i=1,3,5,...
level inverters due to reduced switching losses. In this paper, The proposed basic unit generates 11 levels at the output.
SHEPWM method is used for the computation of switching With 11 levels, four harmonics can be eliminated. Several
angles. The Fourier series for the staircase output voltage combinations of these four harmonic orders can be made to
waveform shown in Fig. 10 is expressed as: be eliminated. Generally, lower order harmonic orders are
ao Xn

2πnt

2π nt
eliminated. In this paper, 3rd , 5th , 7th , and 9th order harmonics
vo (t) = + an cos + bn sin are chosen to eliminate from the output voltage waveform
2 i=0 T T
of the proposed MLI. In SHEPWM technique, firing angles
(76)
(θ 1 , θ2 , . . . , θ5 ) are calculated using (79) by maintaining the
where ao , an , and bn represents the dc, even harmonic and relationship (0 < θ 1 < θ2 , . . . , < θ 5 < π 2) (79), as shown
odd harmonic components of the output voltage respectively, at the bottom of the next page.
and n is the harmonic order. As the staircase output voltage Where b1 = V D is the fundamental component and gives
have quarter wave symmetry, ao , an and sine terms of odd the desire output voltage VD . b3 , b5 , b7 , andb9 are the

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M. D. Siddique et al.: Optimal Design of a New Cascaded MLI Topology With Reduced Switch Count

FIGURE 12. Experimental Setup.

TABLE 3. Switching angles for 11 levels (ma = 0.8).

FIGURE 11. Variation of (a) switching angles and (b) harmonics with
variation in modulation index.

VII. RESULTS AND DISCUSSION

The performance of the proposed multilevel inverter is inves-
harmonic orders to be eliminated and made equal to zero. The tigated by designing a prototype experimental setup. The
modulation index is given by, proposed basic unit along with its cascade connection are
π × VD designed and results for 11 and 71 levels are provided in
ma = (80) this manuscript. For the 11 level generation, SHE PWM is
2 × (N − 1) × Vdc
used for the gate pulse generation as angles given in Table 3.
The solution of (79) and (80) gives the switching angle For the cascade connection with 71 levels, selective harmonic
used for the generation of gate pulses. For the proposed elimination PWM technique is used for gate pulse generation
inverter, optimized switching angles are calculated using the due to its easy implementation and all the switching angles
PSO algorithm described in [9]. Table 3 gives the different are given in Table 4. All these angles are calculated offline.
switching angles for the 11 level output voltage. Fig. 12 shows the hardware setup for the proposed cascade
The variation of these switching angles with modulation MLI. TOSHIBA IGBT GT50J325 with an antiparallel diode
index ma is depicted in Fig. 11 (a). Fig. 11 (b) shows the is used for the prototype setup, while dSPACE is used for the
variation of different harmonic orders with modulation index. gate pulse generation for the switches.
On a similar way, for the cascade connection of two mod-
ules, SHE is implemented for 71 level. For 71 levels, all the A. EXPERIMENTAL RESULTS FOR THE BASIC UNIT
harmonics from 3rd to 69th are considered for the elimination Basic unit is used for the generation of 11 levels at the output.
and the switching angles are provided in Table 4. The selection of the magnitude of dc voltage sources is based

4Vdc

b1 = [cos (θ1 ) + cos (θ2 ) + cos (θ3 ) + cos (θ4 ) + cos (θ5 )] = VD 
π




4Vdc


[cos (3θ 1 ) + cos (3θ2 ) + cos (3θ3 ) + cos (3θ4 ) + cos (3θ5 )] = 0 

b3 = 
3π




4Vdc 
b5 = [cos (5θ1 ) + cos (5θ 2 ) + cos (5θ 3 ) + cos (5θ4 ) + cos (5θ 5 )] = 0 (79)
5π 

4Vdc 
[cos (7θ 1 ) + cos (7θ2 ) + cos (7θ3 ) + cos (7θ4 ) + cos (7θ5 )] = 0 

b7 = 
7π




4Vdc 
[cos (9θ 1 ) + cos (9θ2 ) + cos (9θ3 ) + cos (9θ4 ) + cos (9θ5 )] = 0 

b9 =


9π

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M. D. Siddique et al.: Optimal Design of a New Cascaded MLI Topology With Reduced Switch Count

FIGURE 14. Output voltage waveform Vo with voltage stress across

switches (a) S1 , S3 , and V5 (b) S4 , S6 , and V11 .

TABLE 4. Switching angles for 71 levels (ma = 0.8).

SHEPWM at the modulation index of 0.8. The calculated

FIGURE 13. Experimental results for basic unit (a) output voltage angles are provided in Table 3. Fig. 13 (a) illustrates the
waveform and (b) FFT of output voltage (c) Output voltage and current
waveform with R load and (d) Output voltage and current waveform with output voltage of the basic unit with 11 levels at the output.
RL load. The 3rd , 5th , 7th , and 9th harmonic orders are selected to be
eliminated from the output voltage waveform. Fig. 13 (b)
on MODE I i.e. V1 = 50V and V2 = 100V. The peak voltage demonstrates the FFT of the output voltage. It is clear from
generated at the output is 250V, with a voltage step of 50V and Fig. 13 (b) that all selected harmonic orders are eliminated
50Hz output frequency. The gate pulses are generated using from the output voltage.

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M. D. Siddique et al.: Optimal Design of a New Cascaded MLI Topology With Reduced Switch Count

FIGURE 15. (a) Output voltage of first module (20V/div) (b) zoomed
voltage view (20V/div) of first module and (c) output voltage of second
module with 100V/div.

The performance of the proposed basic unit is checked by

connecting different types of load. Fig. 13 (c) shows the out-
put voltage and current waveform for a purely resistive load
having a value of 100. Fig. 13 (d) displays the voltage and
current waveform with series connected resistive-inductive
load with R = 80 and L = 200mH. Both output voltage
waveforms are of 50Hz with 11 levels at the output. FIGURE 16. (a) Output voltage of two cascaded modules across the load,
(b) zoomed view of the output voltage waveform, (c) FFT of the output
Fig. 14 (a) – (b) show the voltage stress of different voltage waveform and (d) load current with RL load.
switches of the basic unit. The voltage stress across switch S1
is the maximum with a value of 250V. The pattern of voltage S5 is 200V and 50V, respectively, as indicated in Fig. 14 (a).
stress across switch S2 is the same as that of S1 with the Fig. 14 (b) shows the voltage stress variation of switches S4 ,
magnitude of 250V. The voltage stress across switches S3 and S6 and bidirectional switch S11 with output voltage Vo .

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M. D. Siddique et al.: Optimal Design of a New Cascaded MLI Topology With Reduced Switch Count

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[24] R. S. Alishah, D. Nazarpour, S. H. Hosseini, and M. Sabahi, ‘‘Novel topolo- SAAD MEKHILEF (M’01–SM’12) received the
gies for symmetric, asymmetric, and cascade switched-diode multilevel B.Eng. degree in electrical engineering from the
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Trans. Ind. Electron., vol. 61, no. 10, pp. 5300–5310, Oct. 2014. the master’s degree in engineering science and the
[25] E. Babaei, M. Sarbanzadeh, M. A. Hosseinzadeh, and C. Cecati, ‘‘A new Ph.D. degree in electrical engineering from the
basic unit for symmetric and asymmetric cascaded multilevel inverter with University of Malaya, Kuala Lumpur, Malaysia,
reduced number of components,’’ in Proc. 42nd Annu. Conf. IEEE Ind. in 1998 and 2003, respectively, where he is cur-
Electron. Soc. (IECON), Florence, Italy, Oct. 2016, pp. 3147–3152.
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Electronics and Renewable Energy Research Lab-
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pp. 3109–3118, Nov. 2011. has authored or co-authored over 400 publications in international journals
[27] E. Babaei and S. Laali, ‘‘Optimum structures of proposed new cascaded and conference proceedings. His current research interests include power
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[29] E. Babaei, ‘‘A cascade multilevel converter topology with reduced number in 1999, the M.Eng. degree from Oita University,
of switches,’’ IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2657–2664, Japan, in 2003, and the Ph.D. degree from George
Nov. 2008.
Mason University, Fairfax, VA, USA, in 2014. She
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is currently a Senior Lecturer with the Department
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version,’’ IEEE Trans. Ind. Electron., vol. 61, no. 8, pp. 4011–4021, of Electrical Engineering, University of Malaya.
Aug. 2014. Her current research interests include signal pro-
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modulation for cascaded multilevel inverters,’’ IEEE Trans. Ind. Electron.,
vol. 65, no. 3, pp. 2828–2833, Mar. 2018.

MUDASIR AHMED MEMON received the B.E.

degree in electronics engineering and the M.E.
degree in electronic systems engineering from the
MARIF DAULA SIDDIQUE (S’18) was born Mehran University of Engineering and Technol-
in Chhapra, India, in 1992. He received the ogy, Jamshoro, Pakistan, in 2009 and 2015, respec-
B.Tech. and M.Tech. degrees in electrical tively. He is currently pursuing the Ph.D. degree in
engineering from Aligarh Muslim University, power electronics with the University of Malaya,
in 2014 and 2016, respectively. He is currently pur- Malaysia.
suing the Ph.D. degree with the Power Electron- From 2009 to 2016, he was a Lecturer and then
ics and Renewable Energy Research Laboratory, an Assistant Professor with the Institute of Infor-
Department of Electrical Engineering, University mation and Communication Technology, University of Sindh, Jamshoro. His
of Malaya, Kuala Lumpur, Malaysia. His research research interests include multilevel inverters, power quality, and control
interests include step-up power electronics con- strategies.
verters (dc/ac and dc/dc), and multilevel inverter topologies and their control.

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