World Academy of Science, Engineering and Technology

International Journal of Electronics and Communication Engineering

Vol:3, No:2, 2009

Uniform Overlapped Multi-Carrier PWM for a

Six-Level Diode Clamped Inverter
S.Srinivas

drawbacks, they have their own merits as compared to the

Abstract—Multi-level voltage source inverters offer several others. These circuits are slowly being accepted by the
advantages such as; derivation of a refined output voltage with industry in the recent times and are the focus of many
reduced total harmonic distortion (THD), reduction of voltage ratings researchers now.
of the power semiconductor switching devices and also the reduced
Several multilevel PWM switching schemes have been
electro-magnetic-interference problems etc. In this paper, new
carrier-overlapped phase-disposition or sub-harmonic sinusoidal proposed in the past and an extensive survey of PWM
Open Science Index, Electronics and Communication Engineering Vol:3, No:2, 2009 waset.org/Publication/6702

pulse width modulation (CO-PD-SPWM) and also the carrier- schemes has also been reported in the literature [7]. Improved
overlapped phase-disposition space vector modulation (CO-PD- spectral performance and enhanced DC-bus utilization is also
SVPWM) schemes for a six-level diode-clamped inverter topology achieved by altogether modifying the sinusoidal modulating
are proposed. The principle of the proposed PWM schemes is similar signal by either adding appropriate third harmonic component
to the conventional PD-PWM with a little deviation from it in the
or giving suitable offset voltages [7]-[9]. Triangular multi-
sense that the triangular carriers are all overlapped. The overlapping
of the triangular carriers on one hand results in an increased number carriers are uniformly distributed with their phases adjusted to
of switchings, on the other hand this facilitates an improved spectral suit the application is reported in the past [10]-[13]. Multilevel
performance of the output voltage. It is demonstrated through PWM with modified triangular carriers are also reported in the
simulation studies that the six-level diode-clamped inverter with the literature for a multi-level inverter [14]-[15].
use of CO-PD-SPWM and CO-PD-SVPWM proposed in this paper is In this paper, uniform, zero phase shifted, overlapped multi-
capable of generating multiple levels in its output voltage. The
carrier PWM switching schemes are proposed using the
advantages of the proposed PWM schemes can be derived to benefit,
especially at lower modulation indices of the inverter and hence this conventional SPWM and also the SVPWM for a six-level
aspect of the proposed PWM schemes can be well exploited in high diode-clamped inverter circuit topology. It is eloquently
power applications requiring low speeds of operation of the drive. demonstrated through simulation studies that the spectral
performance of the output voltage using the overlapped carrier
Keywords—Diode clamped inverter, Pulse width modulation, PWM proposed in this paper is improved as compared to the
Six level inverter, carrier based PWM. use of the conventional PD-PWM especially in the lower
modulation range. The main drawback with the use of the
I. INTRODUCTION proposed PWM is the increased total number of switchings;

R ESEARCH on various multi-level inverter power circuit

topologies has extensively increased ever since the
neutral-point-clamped three-level inverter configuration was
resulting in an increased switching power loss. However, the
improved spectrum of the output voltage with the proposed
PWM scheme could offset the increased switching power loss.
first introduced by Nabae et.al. [1]. The multi-level inverters
offer several advantages such as, less stresses on the switching II. DIODE-CLAMPED SIX-LEVEL INVERTER
devices, less THD in the output of the inverters, less ripple in The schematic of the three-phase six-level diode-clamped
the output voltage and a better spectral performance of the inverter configuration is shown in Fig.1. Each of the three
inverters etc. It was demonstrated that, refined output voltage phases of the inverter, share a common DC-bus, which has
can be obtained either by using smaller imbricated cells or the been subdivided into six levels, using five capacitors. The
cascaded inverter structures [2]-[6]. H.Stemmler and voltage across each capacitor is equal to a voltage of V DC 5 ,
P.Guggenbach through their research synthesized three-level
and the voltage stress across each switching device is
output by using series cascading of two two-level inverters
therefore limited to V DC 5 through the clamping diodes. The
using induction motor with open-end stator windings [5].
Recently, it was established that using cascaded retrofit of two output voltage levels possible for one phase of the inverter
two-level inverters, three-level output voltage can also be (Fig.1) with the negative dc rail voltage ‘ V0 ’ (equal to zero
synthesized [6]. While each of the proposed circuits has some volts), taken as the reference are tabulated and presented in
Table-I. In Table-I, a ‘P’ means, the switch is turned ON and
an ‘N’ means, the switch is turned OFF. In Fig.1, each phase
S.Srinivas is with the Department of Electrical Engineering, Indian has five complementary switch pairs such that turning-on one
Institute of Technology Madras, Chennai, Tamilnadu, INDIA - 600 036
(phone: +91-44-2257 4447; fax: +91-44-2257 4402; e-mail: of the switches of the pair require that the corresponding
[email protected]).

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Vol:3, No:2, 2009

complementary switch be turned off and vise-versa. The

complementary switch pairs for a-phase limb are (SWa1,
SWa1’), (SWa2, SWa2’), (SWa3, SWa3’), (SWa4, SWa4’), and
(SWa5, SWa5’). Table-I, also shows that in a diode-clamped
inverter, the switches that are turned on for a particular phase
limb are always adjacent and in series. It is known that in a
six-level diode-clamped inverter topology, a set of five
switches are turned on at any given point of time.
The line voltage V AB consists of a-phase limb voltage and
b-phase limb voltage. The resulting line voltage is an eleven
level staircase waveform [11]. This means that an m-level
diode-clamped inverter has an m-level output phase voltage
and a (2m-1)-level output line voltage [11]. Although each
active switching device is required to block only a voltage
level of V DC 5 , the clamping diodes require different ratings
for reverse voltage blocking. In phase ‘a’ (Fig.1), when all the
Open Science Index, Electronics and Communication Engineering Vol:3, No:2, 2009 waset.org/Publication/6702

lower switches SWa1’ through SWa5’ are turned-on, D4 must

block four voltage levels or 4 V DC 5 . Similarly, D3 must
block 3 V DC 5 , D2 must block 2 V DC 5 and D1 must
block V DC 5 . If the inverter is designed such that each
Fig. 1 Schematic of the six-level diode-clamped inverter
blocking diode has the same voltage rating as the active configuration
switches, Dn will require ‘n’ diodes in series; consequently,
the number of diodes required for each phase would be (m-1) TABLE- I SIX-LEVEL DIODE-CLAMPED INVERTER VOLTAGE
× (m-2). Thus, the number of blocking diodes is quadratically LEVELS AND CORRESPONDING SWITCH STATES
related to the number of levels in a diode-clamped converter V4= V3= V2= V1=
Voltage V5= V0=
[11]. 4V DC 3V DC 2V DC V DC
V AO V DC 0
5 5 5 5
III. MULTILEVEL CARRIER-BASED PWM SWa5 P N N N N N
SWa4 P P N N N N
Principles of several two-level carrier-based PWM SWa3 P P P N N N
techniques have been extended as means of controlling the SWa2 P P P P N N
active devices in a multilevel converter. The most popular SWa1 P P P P P N
SWa5’ N P P P P P
control technique for traditional two-level inverters is the
SWa4’ N N P P P P
sinusoidal or “sub-harmonic” natural pulse width modulation SWa3’ N N N P P P
method which uses several triangle carrier signals and one SWa2’ N N N N P P
reference or modulation signal per phase. Its popularity is due SWa1’ N N N N N P
to its simplicity and the good results it guarantees in all the
operating conditions, including over-modulation which allows
of carrier-based PWM techniques adopting SPWM are applied
first harmonic amplitude up to (4 /Π) p.u. In order to achieve
to a multilevel inverter and are reported in the literature as
enhanced DC-bus utilization and also improved spectral
phase opposition (PO), alternate phase opposition disposition
performance, the modified reference signal is adopted, using
(APOD) and sub-harmonic or phase disposition (PD) [10]-
sinusoidal fundamental along with third harmonic injection of
[11].
an appropriate magnitude or with appropriate offset voltages.
It is known that in the case of a conventional two-level
The three multilevel PWM methods most discussed in the
inverter, each leg of the inverter can attain two voltage levels
literature for the multi-level inverters have been multilevel
depending on whether the top switching device is turned on or
carrier-based PWM, selective harmonic elimination, and
the bottom switching device. Hence, the two-level three phase
multilevel space vector PWM; all are extensions of traditional
inverter has a total of 23 i.e. eight switching combinations;
two-level PWM strategies to several levels. Several variations
spread around 7 space locations; forming a regular hexagon
shown in Fig.2 (each side equal to the DC-bus voltage ‘ V DC ’
of the two-level inverter). In the case of the six-level diode-
clamped inverter (Fig.1), each phase pole voltage (for instance
V AO shown in Table-I) can attain six levels independent of the
other. Therefore, a total of 63 i.e. 216 switching combinations
are possible that are spread

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Fig. 2 Space locations of the conventional two-level inverter

Fig. 4 Principle of the PD-SPWM and the derived

pole voltage replica with the use of PD-SPWM
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It gives an output of ‘+1’ if the modulating signal is greater

than the triangular carrier and an output of ‘0’ when the
modulating signal is lesser than the triangular carrier. It is
generally accepted that with the use of PD-PWM strategy, the
THD in the output voltage is less as compared to the CO-
PWM and APOD-PWM [10]. The principle of the
conventional PD-SPWM along with the resulting pole-voltage
replica for a single phase is shown in Fig.4. Now, to comply
with the requirements for a three-phase system, three 1200
phase-shifted modulating sinusoids are compared with the
level shifted triangular carrier set under single-phase
modulation technique.
Fig. 3 Space vector locations of the six-level
diode-clamped inverter IV. CARRIER-OVERLAPPED SUB-HARMONIC OR PHASE DIPOSITION PWM
FOR A SIX-LEVEL DIODE-CLAPED INVERTER

In the context of the present six-level diode-clamped

around 91 space locations shown in Fig.3. For instance, the
inverter (Fig.1), the six-level carrier PWM is presented using
switching combination (5,5,0) means that the a-phase and b-
the over-lapped, level-shifted, uniform zero phase-shifted,
phase pole-voltage output is equal to V DC each and the c-phase
triangular carrier signals. Everything else remains the same, as
pole-voltage output is 0 volts. Substituting these conditions in in the conventional PD-SPWM, but for the overlapped
the expression for the space vector, given by equation (1) and triangular carrier signals. The principle of the proposed
simplifying; results in the space location number 67 (Fig.3).
carrier-overlapped phase-disposition SPWM (CO-PD-SPWM)
The locations for the remaining switching combinations can
along with the derived pole voltage replica for a single phase
be similarly obtained.
of the six-level inverter is shown in Fig.5. From Fig.5, it may
VS = v AO + v BO × e j ( 2π / 3) + vCO × e j ( 4π / 3) (1) be seen that the total number of switchings in the phase is
increased (doubled) as compared to the number of switchings
For the six-level PWM method, triangular carrier signals shown in Fig.4 (using the conventional PD-SPWM) for the
keeping only one modulating sinusoidal signal is taken. same frequency and amplitude modulation.
Conventionally, it is well known that if an N-level inverter is
employed, (N–1) carriers will be needed [10]. The carriers The principal advantage with the proposed CO-PD-SPWM
have the same frequency ‘ωc’, and the same peak-to-peak is that the spectral performance of the output voltage is
amplitude A, are disposed so that the bands they occupy are considerably improved. It is indisputable that increasing the
contiguous. The modulating signal is a sinusoid of frequency switching frequency would alienate the lower order harmonics
‘ωm’, and amplitude Am. At every instant each carrier signal is and improve the spectral performance of the output voltage.
compared with the modulating signal. Each comparison gives
two logic outputs depending on the instantaneous magnitudes
of the modulating sinusoid and the carrier signal.

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Fig. 5 Principle of the proposed CO-PD-SPWM approach and the Fig. 6 CO-PD-SVPWM approach and the derived pole voltage
derived pole voltage replica with the proposed CO-PD-SPWM replica with the proposed CO-PD-SVPWM
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In order to draw attention onto the significance of the the largest circle inscribed in the hexagon shown in Fig.2).
proposed PWM scheme and for proper comparison, the phase Hence, the frequency of the modulating signal is set equal to
voltage is obtained using the proposed CO-PD-SPWM and 50 Hz with the DC-bus voltage for the six-level inverter taken
also with the conventional PD-SPWM with doubled switching as 100Volts at the modulation depth ‘ma’ equal to 3 2 i.e.
frequency. The normalized harmonic spectra of the phase
0.866 . The modulation depth ‘ma’ is defined as the ratio of
voltage with the double switching frequency using
the magnitude of the space vector and the DC-bus voltage of
conventional PD-SPWM is compared with the results
the inverter. The motor would run at its rated speed
obtained using the proposed CO-PD-SPWM and are shown in
corresponding to the fundamental frequency (‘f1’) of 50Hz at
the later section.
this modulation depth.
As it is known that the use of the SVPWM would improve
A low speed of operation is obtained when the frequency of
the DC-bus utilization, suitable offsets are added to the
the modulating signal ‘f1’ is set low. Corresponding to the
sinusoidal modulating signal and the over-lapped triangular
fundamental frequency f1=20Hz, the switching frequency of
carrier based implementation of SVPWM is also
demonstrated. The CO-PD-SVPWM principle and the derived the inverter would be 420Hz and the modulation depth of the
pole voltage replica of a single phase are shown in Fig.6. inverter would then be equal to 0.3464.
It may be noted that while explaining the principle of The a-phase pole voltage and its normalized harmonic
operation using the schematics (Figs.4, 5, & 6) the modulating spectrum, phase voltage (a-phase) and its normalized
signal is chosen to be of 50Hz. However, in the actual harmonic spectrum all taken when the fundamental frequency
simulation studies shown in the results, a constant V/f control is equal to 20Hz are shown in Fig.7. It can be seen from the
is adopted in the linear modulation zone. normalized harmonic spectra of the a-phase pole voltage
(Fig.7.b) that the burst of harmonics are spread at and around
V. RESULTS & DISCUSSIONS
the multiples of the frequency modulation i.e.21. Similarly,
the results when the fundamental frequency is equal to 40Hz
The uniform, zero phase shifted, carrier-overlapped phase and 50Hz corresponding to two different motor speeds are
disposition or sub-harmonic carrier-based PWM for the multi- respectively shown in Fig.8 & 9. From figures 7.a, 8.a & 9.a,
level inverter (six-level diode-clamped configuration) it can be seen that as the modulation depth increases, the time
proposed in this paper are simulated using the MATLAB period of the pole-voltage is decreased (frequency is
simulation software. The inverter is assumed to feed an increased) because of V/f control.
induction motor load controlled with V/f control in the entire It was mentioned earlier (also evident from Figs.4 and 5)
region of linear modulation and with constant terminal voltage that with the proposed CO-PD-SPM, the number of
(flux weakening operation) in the over-modulation region. switchings has increased which is the main drawback. The
Irrespective of the modulation depth, the frequency of the normalized harmonic spectra of the motor phase voltage using
triangular carrier signal is chosen to be 21 times the the PWM switching strategies proposed in this paper i.e. CO-
fundamental frequency which means that there will be a total PD-SPWM and also the conventional PD-SPWM are shown
of 21 carrier cycles in one entire cycle of the fundamental. It is in Fig.10 for critical comparison (all with f1=20Hz). Though
known that the length of the maximum voltage vector at the the number of switchings increases, it is evident from Fig.10.b
verge of linear-modulation is equal to 3VDC 2 (radius of that there is an improved phase voltage harmonic spectra with
the use of the proposed CO-PD-SPWM method.

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Hence, it demonstrated that the six-level diode-clamped

inverter is capable of generating multiple levels in its output
by changing the modulation depths or the frequency of the
modulating signal (Figs. 7.a, 8.a and 9.a). The principal
advantage with this PWM scheme in fact is improved spectral
performance as compared to the conventional PWM scheme
even though the resulting switchings are more. The results
with the CO-PD-SVPWM scheme proposed for the six-level Fig. 8.a A-phase pole-voltage with f1=40Hz.
diode clamped inverter with the fundamental frequency of
20Hz is presented in Fig.11.
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Fig. 8.b A-phase phase voltage with f1=40Hz.

Fig. 7.a A-phase pole-voltage with f1=20Hz.

Fig. 8.c Normalized harmonic spectrum of the phase voltage with

f1=40Hz.

Fig. 7.b Normalized harmonic spectrum of a-phase pole voltage

with f1=20Hz.

Fig. 9.a A-phase pole-voltage with over-modulation.

Fig. 7.c A-phase phase voltage with f1=20Hz.

Fig. 9.b A-phase phase voltage with over-modulation.

Fig. 7.d Normalized harmonic spectrum of the phase voltage with Fig. 9.c Normalized harmonic spectrum of the phase voltage
f1=20Hz. with over-modulation

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inverter switches demonstrating the multiple levels obtained

from the inverter. The principle difference between the
conventional PD-SPWM and the CO-PD-SPWM is also
discussed and presented. Through simulation studies, it is
demonstrated that the harmonic profile of the phase voltage of
the inverter improves with the use of CO-PD-SPWM scheme
proposed in this paper as compared to the use of the
(a) conventional PD-SPWM, suggesting that the THD in the
output voltage can be reduced. Also, results with the carrier-
based CO-PD-SVPWM are presented that can be used to
improve the DC-bus utilization. Hence, with the proposed
carrier-overlapped PWM scheme, though it is seen that the
number of switchings are increased, it in fact facilitates an
improved spectral performance of the motor phase voltage
especially at low speeds of operation of the motor. This aspect
of the proposed PWM scheme can be exploited in high power
(b)
applications requiring low speeds of operation of the drive.
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REFERENCES
[1] Akira Nabae, Isao Takahashi and Hirofumi Akagi, “A Neutral-Point
Clamped PWM Inverter”, IEEE-Trans. on Ind. Appl. Vol.IA-17, No.5,
Sep/Oct 1981, pp.518-523.
[2] T.A.Maynard and Foch, “Imbricated cells multi-level voltage source
inverters for high power applications”, EPE Journal, Vol.3, No.2, 1993,
pp.99-106.
(c) [3] X.Yuan and I.Barbi “Fundamentals of a new diode clamping multilevel
Fig. 10 Normalized harmonic spectra of the phase voltage with inverter,” IEEE Trans. Power Electronics., vol. 15, pp. 711, Jul. 2000.
[4] J.Rodriguez, J. S.Lai, and F.Z.Peng, “Multilevel Inverters: A Survey of
f1=20Hz.using (a) conventional PD-SPWM (b) CO-PD-SPWM topologies, Controls, and Applications,” IEEE Trans. on Ind.
proposed in this paper & (c) conventional PD-SPWM and double the Electronics, Vol 49, No.4, August 2002, pp.724 - 738.
switching frequency [5] H.Stemmler, P.Guggenbach," Configurations of High-Power Voltage
Source Inverter Drives", Proc. EPE Conf., 1993, pp.7 - 14.
[6] V.T.Somasekhar and K.Gopakumar, “Three-level inverter configuration
cascading two-level inverters”, IEE Proc. of Electr. Power Appl.,
Vol.150, No.3, May 2003, pp.245-254.
[7] J.Holtz, “Pulsewidth modulation- A survey”, IEEE Trans. on Industrial
Electronics, Vol. 30, No. 5, Dec 1992, pp. 410-420.
[8] Dae-Woong Chung, Joohn-Sheok Kim and Seung-Ki Sul, “Unified
Voltage Modulation Technique for Real-Time Three-Phase Power
Conversion”, IEEE-Trans. on Ind.Appl, Vol.34, No.2, March/April
1998, pp.374-380.
[9] B.P.McGrath, D.G.Holmes and T.Meynard, “Reduced PWM Harmonic
(a) Distortion for Multilevel Inverters Operating over a Wide Modulation
Range”, IEEE Trans. on Power Electronics, vol. 21, no.4, July 2006, pp.
941-949.
[10] G.Carrara, S.Gardella, M.Marchesoni, R.Salutari, G.Sciutto, “A New
Multilevel PWM Method: A Theoretical Analysis,” IEEE Trans. on
Power Electronics, vol. 7, no. 3, July 1992, pp. 497-505.
[11] L.M.Tolbert, and T.G.Habetler, “Novel Multilevel Inverter Carrier-
Based PWM Method”, IEEE-Trans. on Ind.Appl, Vol.35, No.5,
Sept./Oct 1999, pp.1098-1107.
[12] L.Li.D.Czarkowski, Y.Liu and P.Pillay, “Multilevel space vector PWM
technique based on phase-shift harmonic suppression,” in Proc. IEEE
(b) Annu. APEC Conf., 2000, Vol.1, pp. 535-541.
Fig. 11.(a) A-phase phase voltage (b) Normalized harmonic [13] B.P.McGrath and D.G.Holmes, “Multicarrier PWM strategies for
spectrum of the a-phase voltage using the CO-PD-SVPWM proposed multilevel inverters”, IEEE Trans. on Power Electronics, vol. 49, no.4,
in this paper with f1=20Hz. Aug 2002, pp. 858-867.
[14] P.C.Loh, D.G.Holmes, Y.Fukuta and T.A.Lipo, “Reduced Common-
Mode Modulation Strategies for Cascaded Multilevel Inverters”, IEEE-
VI. CONCLUSION Trans. on Ind.Appl, Vol.39, No.5, Sept./Oct 2003, pp.1386-1395.
[15] R.Naderi and A.Rahmati, “Phase-Shifted Carrier PWM Technique for
In this paper, uniform zero phase shifted carrier-overlapped General Cascaded Inverters”, IEEE Trans. on Power Electronics, vol.23,
multilevel PWM scheme are proposed for a six-level diode- no. 3, May 2008, pp. 1257-1269.
clamped inverter topology. The overlapped carrier, sub-
harmonic or CO-PD-SPWM and also CO-PD-SVPWM
methods are presented to control the six-level diode-clamped

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