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Three-phase three-level voltage source inverter with low switching frequency

based on the two-level inverter topology

Article  in  IET Electric Power Applications · August 2007

DOI: 10.1049/iet-epa:20060280 · Source: IEEE Xplore

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Three-phase three-level voltage source inverter
with low switching frequency based on the
two-level inverter topology
E.A. Mahrous, N.A. Rahim and W.P. Hew

Abstract: A new configuration of the three-phase three-level voltage source inverter has been
presented. The proposed inverter is based on the two-level inverter. The inverter is built of one
two-level conventional inverter, an auxiliary circuit which comprises of three bidirectional
switches, and two bulk capacitor banks. A selected harmonic elimination control scheme is
employed to achieve lower harmonic contents in the inverter output waveforms. Two-level inverter
switches operate at the line power frequency (50 Hz) whereas the auxiliary circuit switches operate
at twice line power frequency (100 Hz). To validate the proposed inverter, a low power prototype
inverter has been designed and implemented; analytical, simulation and experimental results have
been provided.

1 Introduction the conventional full-bridge type two-level inverters. In

recent years, some new single phase inverter topologies
Two-level three-phase voltage source inverter is the most have been proposed to improve the performance of the con-
commonly used topology in today’s motor drives. In case ventional single– phase full-bridge inverter [11, 12] by
of single switching per cycle, six-step modulations, the adding two switching elements and two main diodes [11]
control of the circuit is accomplished by varying the turn or simply adding one bidirectional switching element
on time of the upper and lower switches of each inverter [12], which yields in increasing the number of its output
leg, with the provision of never turning on both switches waveform voltage levels compared to the conventional
at the same time, to avoid a short circuit of the DC bus. inverter; however the proposed configurations are for
Such a way of creating the output waveform has some single-phase inverter, whereas this paper proposes a three-
pros and drawbacks. The control circuit by this method is phase three-level voltage source inverter topology based
simple and the switching losses are almost negligible, on the two-level three-phase inverter.
besides the modulation index is high. However, such a The paper will begin in Section 2 with describing and
control method is rarely applied in practice because of the explaining the proposed inverter general block diagram,
high value of the output harmonic contents, where the inverter configuration, its operating principles and control
total harmonic distortion (THD) ratio is approximately pulses needed for operating inverter switches. Section 3
31% [1]. subsequently presents the selected harmonics elimination
In general, there are some proposed solutions in [1 – 3] (SHE) control method and the inverter output waveform
focus on an attempt to add the output of more than one THD minimisation analysis. Serving as a reference for
cell of the two-level inverter using injection transformers inverter validity, Section 4 gives Matlab simulated results
or directly by connecting the output of one cell in series and laboratories measurements. These results are used for
with another [4, 5]. Also another solution can be found in verifying the performance of the proposed three-level inver-
multilevel inverters (MLIs) [6– 9] and [10]. In MLIs, ter prototype whose analysis is presented in Section 2. Last,
switches are connected in parallel and series in order to Section 5 summarises the proposed inverter concepts
provide high power demand and high power quality. In presented in the paper.
addition to the switching frequency of these devices can
be as low as line power frequency making the problem of 2 Proposed inverter topology, configuration and
both EMI and devices voltage stress to be nearly absent. operational principles
Neutral point clamped (NPC) three-phase inverter [9],
which is widely used in industrial applications, uses four The block diagram of the proposed three-phase three-level
switching elements and two clamping diodes in each arm. voltage source inverter system consists from two isolated
It has three-level voltage waveforms: zero, positive and and regulated DC sources, proposed three-level inverter,
negative supply DC voltage level that results in consider- microcontrollers, data acquisition card PCL-818L and a per-
able suppression of the harmonic currents comparing with sonal computer as shown in Fig. 1. This system acts as a link
between the output of the linear generator and the load,
# The Institution of Engineering and Technology 2007 where the linear generator output voltage is single-phase
doi:10.1049/iet-epa:20060280 distorted waveform with frequency varying from 25 to
Paper first received 5th July 2006 and in revised form 16th February 2007 50 Hz. Because of that it is not suitable for many appli-
The authors are with the Faculty of Engineering, University of Malaya, cations, which use 50 Hz AC. The inverter output voltage
KL 50603, Malaysia can be controlled by controlling the DC inverter bus link
E-mail: [email protected] voltages, where two DC-DC boost converter circuits with
IET Electr. Power Appl., 2007, 1, (4), pp. 637 –641 637

Authorized licensed use limited to: Raghu Engineering College. Downloaded on February 6, 2009 at 04:14 from IEEE Xplore. Restrictions apply.
Fig. 1 Block diagram of the proposed inverter and the feedback
control circuit

Fig. 3 Switching timing diagram

10 kHz switching frequency have been used. The measured
voltages of the inverter DC capacitor link (two analogue
signals) from the sensors are received first by microcontrol- In addition to the boost topology used with a single
ler 1 and microcontroller 2, which convert them to 8 bits switch, it has high efficiency [15].
digital signals for each analogue signal (16 bits total). In order to explain how the staircase voltage is syn-
These 16 digital bits are received by the PC through the thesised, the neutral point n is considered as the output
PCL-818L card. phase voltage reference point and by applying the switching
The digital data are processed in real time to calculate the patterns given in Fig. 3, the node a referred to point n can be
duty cycle of each DC-DC converter using PID controller, defined as follows:
which is commonly and widely used. The sampling fre-
quency is chosen to be 2 kHz, which is fast enough to † For voltage level van ¼ Vdc , turn on the upper switch Q1 .
perform these calculations. These duty cycles subsequently † For voltage level van ¼ Vdc/2, turn on the middle switch S1 .
are sent back to the hardware through the PCL-818L card in † For voltage level van ¼ 0, turn on the lower switch Q2 .
a digital form. Microcontroller 1 and Microcontroller 2
receive these digital data from the PCL-818L card and The three-phase load node voltages van , vbn and Vcn ,
convert them to a duty cycle required by each switch in which shown in Fig. 4 can be represented by a space
the DC-DC converter. Microcontroller 3 is used to generate vector in a a – b transformation
the inverter nine controlling pulses. In order to avoid short
circuit during transition between switches of a phase a 2
V ¼ (van þ a vbn þ a2 vcn ) (1)
proper time delay has been considered. 3
Fig. 2 shows the proposed inverter. It can be noticed
that this inverter consists of two isolated H-bridge circuit where a is the complex operator
units, and capacitor banks Ctop and Cbot , respectively, con- pffiffiffi
ventional two-level inverter Q1 to Q6 as a main inverter at 1 3
a¼ þj
50 Hz switching frequency, and an additional circuit 2 2
which compromises of bidirectional (middle) switches S1
to S3 , at 100 Hz switching frequency, which allows
Placing voltages Fig. 4 into (1) yields a set of 12 active
energy to flow in both directions, similar to the NPC inver-
switching state vectors u1 , . . . , u12 as shown in Fig. 5 The
ter [9, 13].
switching vectors are grouped in two groups, large and
The efficiency of the whole converter circuit is high
small vectors. Large space vectors are represented by
which attributed to the inverter switches operate at low
odd vectors, that is, u1 , u3 , u5 , u7 , u9 and u11 , whereas
switching frequencies (where the total switching times are
small space vectors are represented by even vectors, that
much less than the period); this will result in switching
is, u2 , u4 , u6 , u8 , u10 and u12 . Obviously one can note
losses of the inverter circuit to be negligible [14].

Fig. 2 Proposed nine switches three-level inverter Fig. 4 Load node voltages van , vbn and vcn

638 IET Electr. Power Appl., Vol. 1, No. 4, July 2007

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Fig. 5 Switching state vectors
Fig. 6 Output line-to-line voltage waveform

that the proposed inverter space vector consists of two

space vectors, the large and small space vectors which For waveform symmetry, (8) must be satisfied. Solving (7)
represent the main and the auxiliary inverters, and (8) by an iteration method gives a1 ¼ 128 and
respectively. a2 ¼ 488.
With reference to Fig. 4, although each phase voltage By having a1 and a2 known, the conduction angles of
referred to the neutral of the DC bus has three-level upper, lower and bidirectional switches u1 , u2 and u3 ,
0, Vdc =2 and Vdc , it can be concluded that the respectively, can be calculated by using (2), (3) and (4). It
line-to-line voltages vab , vbc and vca have five-level was found that the conduction angle of the upper switch
voltages such as 0, Vdc =2, Vdc , Vdc =2 and Vdc . equals the conduction angle of the lower one for each arm
Fig. 6 shows the output line-to-line voltage waveform (i.e. u1 ¼ u2 ¼ 1448), whereas the conduction angle of
of vab . the middle u3 ¼ 728 and this satisfies that u1 þ u2 þ
The switches conduction angles can be calculated as in 2u3 ¼ 3608. Switch current ratings referred to the load
Fig. 4 as follows line current and switch voltage ratings referred to the DC
inverter bus voltage Vdc that have also been studied.
4p Table 1 gives these results. It has been found that switches
u1 ¼ 2 a2 , for upper switches Q1 , Q3 and Q5 (2) Q1 , Q2 , Q3 , Q4 , Q5 and Q6 have the same ratings and it is
3
4p much greater than middle switches S1 , S2 and S3 ratings.
u2 ¼ 2p þ 2 a1 , for lower switches Q2 , Q4 and Q6 (3) The effect of optimised angles (a1 and a2) on the THD
3 and the modulation index is shown in Figs. 7a and b,
u3 ¼ 2(a2 a1 ) for bidirectional switches S1 , S2 and S3 : (4) respectively. From these curves, it can easily concluded
that the modulation index varies from about 0.95 to 1.12.
Therefore u1 þ u2 þ u3 ¼ 3608 However, the THD varies from maximum value approxi-
mately 31% at a1 ¼ 08 passing with the minimum value
(optimum operation) approximately 15.5% at a1 ¼ 128, to
3 SHE technique maximum value approximately 31% again at a1 ¼ 308.
From this, it can be concluded that the modulation index
From Fig. 4 which illustrates the load phase voltages can be controlled within the range 0.95 – 1.12, with the
van , vbn and vcn referred to the neutral of the DC bus difference of 0.17. By comparing the proposed inverter
where the line-to-line load voltage vab can be obtained, which consists of 9 power switches and 12 main power
and is governed by the following equation diodes with the three-level NPC inverter which consists of
12 main power switches and 6 main power diodes [13]
vab ¼ van vbn (5) under fundamental frequency modulation, it can be
From (5), the line-to-line voltage vab can be evaluated and
drawn as shown in Fig. 6. This waveform of Fig. 6 is
known as a stepped waveform and is performed as five-level Table 1: Current and voltage ratings for inverter
inverter type. A Fourier analysis of this waveform gives the switches
magnitudes of the harmonics as a function of a1 and a2 as
shown in (6) RMS current ratings Maximum
current ratings
4(Vdc =2)
bn ¼ { cos (na1 ) þ cos (na2 )} upper %(Iswitch/ILoad)RMS ’ 70 %(Iswitch/ILoad)max ¼ 100
np (6)
switch
n ¼ 1, 3, 5, . . .
lower %(Iswitch/ILoad)RMS ’ 70 %(Iswitch/ILoad)max ¼ 100
With the appropriate choice of the conducting angles a1 switch
and a2 , the third and fifth can be eliminated. This can be middle %(Iswitch/ILoad)RMS ’ 9 %(Iswitch/ILoad)max ’ 30
done by equating their harmonic magnitudes to zero as
switch
follows
RMS voltage ratings max voltage ratings
2V upper %(Vswitch RMS/Vdc) ’ 66 %(Vswitch max/Vdc) ¼ 100
b3 ¼ dc {cos(3a1 ) þ cos(3a2 )} ¼ 0
3p switch
(7)
2Vdc lower %(Vswitch RMS/Vdc) ’ 66 %(Vswitch max/Vdc) ¼ 100
b5 ¼ {cos(5a1 ) þ cos(5a2 )} ¼ 0
5p switch
In order to generate a three-phase balanced system vab , vbc middle %(Vswitch RMS/Vdc) ’ 43 %(Vswitch max/Vdc) ¼ 50
and vca , as in Fig. 4, the equation can be observed as switch

(4p=3 a2 ) (2p=3 þ a2 ) ¼ 2a1 ) a1 þ a2 ¼ 608 (8) RMS ¼ root mean square; Max ¼ maximum

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Fig. 10 Experimental results of the upper and lower capacitor
bank voltages, respectively (50 V/div) with step change

Fig. 7 Effect of changing the optimising angles a1 (or a2) on the

amplitude of the modulation index and the THD, respectively

concluded that they produce the same output voltage wave-

form performance.

4 Results and discussions

The MATLAB SIMULINK simulation results of the pro-

posed inverter driving a 1 kW induction motor (IM) load
(230 V AC phase input) are presented. Fig. 8 shows the Fig. 11 Experimental results of inverter output line-to-line
DC-link capacitor voltages Vd1 and Vd2 of the DC-DC voltage and inverter line current, respectively (170 V/div and
voltage regulators; they are stepped from 80 to 110 V for 2 A/div) with step change
each capacitor bank at time 100 ms after simulation starting.
Because the voltage of each capacitor is regulated to 80 V breaking system as a mechanical load. The inverter circuit
or 110 V, the total DC-link voltage is maintained at 160 employs insulated gate bipolar transistors (IGBTs) as a
and 220 V, respectively. switch, and each bidirectional switch is built from one
Fig. 9 illustrates the inverter output waveforms of IGBT and four elements of fast diode rectifier. The inverter
line-to-line voltage vab and line current ia because of the switching frequencies are 50 Hz for the main inverter and
change in the input DC bus link voltage. 100 Hz for bidirectional switches. The control circuit
An experimental prototype of the proposed inverter has switching frequency is 10 kHz, which consists from 2
been built and experimentally tested for an IM as a units of DC-DC boost converter.
dynamic inductive load. The rating of this motor is 1 kW Fig. 10 shows a step change in the DC-link capacitor
at a three-phase line-to-line voltage of 400 V and 50 Hz. voltage, where a step change from 80 to 110 V in each
It is D-connected and it has been loaded with a magnetic capacitor bank was performed, thus maintaining 160 and
220 V on the DC bus, respectively. Fig. 11 shows the inver-
ter output waveforms of line-to-line voltage vab and line
current ia , which indicates that the peak value of the
line-to-line voltage changes approximately from 180 to
230 V and the peak value of the line current changes
approximately from 1.4 to 2 A as shown in Fig. 11.

5 Conclusion

This paper presents a nine switches three-phase three-level

voltage source inverter to reduce the harmonic components
Fig. 8 Simulation results of (from top to bottom) top capacitor
bank and bottom capacitor bank voltages, respectively, of the
of output voltage and load current. Its operating principles,
inverter input DC bus voltages with step change after 0.1 s analytical and switches timing chart based on SHE control
scheme are analysed in detail. The modulation index
can be controlled within the range of 0.95 – 1.12. The
proportional-integral-derivative (PID) control is also
designed and implemented in the case of step response.
The dynamic responses of load waveforms because of the
step change are improved. The simulation and experimental
results show that THD of the proposed inverter is consider-
ably alleviated.

6 Acknowledgment

This research is supported by Ministry of Science,

Fig. 9 Simulation results of (from top to bottom) line-to-line Technology and Innovation, Malaysia, under an IRPA
voltage and line current, respectively, with step change after 0.1 s grant.
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