IEEE PEDS 2005

Proposed Nine Switches Five Level Inverter With

Low Switching Frequencies for Linear Generator
Applications
Mahrous E. A., N.A. Rahim, Member, IEEE, W. P. Hew, and K. M. Nor, Senior Member, IEEE
Faculty of Engineering, University of Malaya, 50603 KL, Malaysia

Abstract- The paper proposes and describes the design and This paper describes operating principles of the
operating principles of 5 levels voltage source inverter which acts transfonner-less 5 levels inverter for the linear generator at low
as a link between the output of the linear generator and the load, switching frequency. The proposed inverter consists of
The output frequency of the linear generator varies from 25 to 50 conventional 6 switches two level inverter acting at the line
Hz depending on the load. Due to that, it is not suitable for many power frequency besides another additional circuit consists of
applications, which use 50 Hz ac. This inverter consists of 6 three switches which can operate in both directions, that is
switches (two levels conventional inverter) which operate at the mean they can pass current in the both directions. This inverter
main line power frequency besides an auxiliary circuit consists of has improved output voltage wave shape companng to the
three switches and with one diode in series with one diode. This conventional two level one.
auxiliary circuit operates also at the line power frequency and as
be shown later it acts as an active filter in reducing the harmonic
contents of the output waveform. A prototype has been designed II. PROPOSED NINE SWITCHES FIVE LEVEL INVERTER
and implemented. To asses the proposed inverter, it is compared
with the conventional two level inverter with single switching Figure 1 shows the proposed 9 switches 5 levels inverter,
eesmetr
inverter. Simulation and experimental results are provided to Fgr hw h rpsd9slce
verify the validity of the model. which consists of 9 switches and three diodes, they are divided
into six 6 switches Q, to Q6 for the two level conventional
Keywords: Linear Generator, Multilevel inverter, two levels inverter. Besides 3 additional two ways switches SI to S3, they
conventional inverter. can pass current in the two directions as shown in some the
operations states of Fig. 2. Figure 3 illustrates the switching
I. INTRODUCTION pattems of these switches. From this figure, it is to be noted
Recently, linear electric generators have drawn a special Qi
that through Q6 operate at the line power frequency (here
interest. Standby or emergency generators are often used as line power frequency is 50Hz), and SI through S3 operate at
backup power supplies or buildings, industrial facilities, and double line frequency. The operation of the proposed inverter
power plants in the event of a loss of utility power [I]-[4]. can be divided into 12 switching states; table I gives these
Unfortunately these generators output waveform are not pure states and figure 2 explains one of these states.
sinusoidal in their shapes and their frequencies. So they can't
use directly to feed loads which require fixed frequency.
In order to explain how the staircase voltage is synthesized,
Transformer-less multilevel voltage source inverters the neutral point n is considered as the output phase voltage
are suitable for medium power. Multilevel inverter has drawn reference point. There are three states to synthesize voltage
tremendous interest in the last few decades [5] to [15] they acrossnodeaandn.
allow them to reach the required voltage with low harmonics
without the use of transformer. As the levels increases, the - For voltage level Van = Vdc, turn on the upper switch Qi,
synthesized output waveform has more steps, which produces a SI.
staircase wave that approaches a desired waveform. - For voltage level Van = Vdc/2, turn on the middle
In PWM-controlled inverters, power electronic devices switch SI.
For voltage level Van2 = 0, turn on the lower switch
Q2re onnadOIvt
can be etured and off very fast
at (within
wtm1p) 1 ts). Due that
u toota -

they almost generate high voltage changes (dV/dt) which the Q2

later can produce broadband electromagnetic interference
(EMI). In addition to the current ratings of these devices
decreased significantly according to their data sheets.
Multilevel inverters solved these problems, because in these
inverters the power semiconductors can be turned on and off
very slow (line frequency switching).

0-7803-9296-5/05/$20.00 C) 2005 IEEE 648

QI Q",3
II1

Vdc
n~~~~ ~ SI
2 c
J S3 ~~~~~~~~N
2.~~Fg 1.___ bh rpsdtrepae5lvlNn wthsivre
Q2 Q4 Q6

Fig. 1. The proposed three phase 5 level Nine switches inverter

649 a

Vdc

2 c
S3
~~~~~~~~N
_jQ2 Q~J6
n

Fig. 2. Switching state T2, whereQ4, Q5, and SI are turned on

I I I I ~~~~~~~~~b3
= f2cos( 3aI) +cos( 3a 2)}= 0
rMMMINX ~~~~(2)
~ 8V
~~~~~~~~~~~~~ ~~~

9 .1
m s,=5 s{cos( 5a,)+Cos( 5a2)}= 0
4b5
==~~~~~~~~~~5
SI

Solving equation 2 will give the following values:

12=480 (3)
and
a11 a2 that,
One important restrains values of in order

to get output three phase wavefonns ix and ax2 must satisfy

the follow ing equations:
I' , ; W//fDw//X/ 0 a1+a2=60' (4)
Oms Sms lOms 15ms 20ms
Fig. 6 (a) and (b) show the amplitude of the fundamental
Fig. 3 a Switching patterns of switches component and the total harmonic distortion respectively of the
output waveform versus a, and a2 It can be noted here that
TABLE I the minimum value of the total harmonic distortion (THD
SWITCHING STATES OF SWITCHES
15%) at a 2l2 ,anda2 48 as calculated in equation 3.
- S.|i2. 3 Q| 4|j Qs| Q6 SI S2 S3 Table II gives the harmonic amplitudes of the output waveform
T, 0 1 0 1 1 0 0 0 0foopiuvaeof,ana2
T2 0 0 0 forotimumvaleofalnd2.
T3 1 0 0 1 1 0 0 0 0
T4 1 0 0 1 0 0 00 1
T5 1 0 0 1 0 1 0 0 '0
T6 1 0 0 0 0 1 0 1 0 200V-
T7 1 0 1 0 0 1 0 0 0
T8 0 0 1 0 0 1 1 0 0
T9 0 1 1 0 0 1 0 0 0
TI0 0 1 1 0 0 0 0 0 1
TI, 0 1 1 0 1 0 0 1 0
T12 0 1 0 0 1 0 0 1 0 .
-200V- _L ' - 1
Os Sms lOms 15ms 2Oms
Y V(G1B,N243254)
Time
III. RESULTS AND DISCUSSIONS: Fig. 4 output phase voltage V.,
Fig. 4 and 5 show the output phase voltage Van and the
output line to line voltage Vab respectively according the 200V-
switching states of this inverter. The amplitude of the nth
component of this waveform is expressed by:
lv-
bn
8V
n ir
I cos( na,)1+ cos( na2 n=l,3,5,. (
a2

-lf QOOi
One important thing here is to select values of (a, a2 )in Sss lOss lS-s lOs
order to cancel the dominant harmonics. To cancel the low oV(GiB,G3BI
order harmonics (the third and the fifth harmonics) values of Time
b 3 3) b 5 must Fig. 5 output line to line voltage Vab
) equal zero, i.e:
>
1 --

Ws

a--
24 .--
V

£510 15_
L..... _s
L
(a)

- -:- --- -, - - - - - ~~T- - - - - If - - -

¢I /I~ ~ ~ ~ -20 _ -J1_LD .1_ ,
:

-------

and the THD respectively against a,

TABLE II
THE HARMONIC CONTENTS OF THE OUTPUT VOLTAGE WAVEFORM OF FIGURE 6
~~~~~~~~~
11) 5

al [degree]

Fig. 6 a and b the amplitude of the findamental component -2

(b)
.
L--

T
~~~10 15 a 2
_: 4 5

0D2(
3 l
--

l
-

L
1
10--0o n__
-100-

100-

;'0
2

10-
0-i

04

0.04
SIMULATION RESULTS:

I
~~~~~~~B

- --
0.04
0.05

0.05
C

I2
0.05
-

I
IV.
Simulations have been carried out using SIMULINK on
two different loads; first load is resistive load with
1 lohmlphase. The second load is inductive with 1 lohm+lOmH
/phase. Fig. 7 and 8 show the simulation results for both the
resistive and the inductive loads respectively. Each figure
illustrates the line to line voltage Vab, the phase voltage Va,
and the line current Ia. the total harmonic distortion of the line
current Ia THD = 17.4% in case of the resistive load, while
THD = 5.4% in case of the inductive load.

> 200
A
-

,~~~~ ~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r
_---
0.06

I-

4-I
I
0.06

0.06
- --

, ;---LLIL---1
l
----------

0.07

0.07

0.07
-
0.08

0.08

II
0.08
1 Oms/div
0.09

Fig. 7 A, B, and C line to line voltage V3b, phase voltage V,, and
0.09

0.09
,
0.1

0.11
0.1 0.12
THD =17.4%
III I~ ~ ~ ~ ~ ~ ~ ~ '

0.1
-I
-

0.12 0.11

0.12 0.11
-

I B

Hannonic Harmonic Normalized line current Ia respectively in case of resistive load.

order n amplitude, bn harmonic
amplitude
n=1
_ (fundamental)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1.0487VdC
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1.0
_ _ _ _ _ _ _ _ _ _
200.-r~~~~~~~~~~~00
T -
7 0. O5 0.0088 100 -- :
___9 0 0 0--~-
11 0.0953Vdc 0.0908 ° .100 - - _ I _ _
13 0.0499Vd C 0.0475 * 200 _ _ -L L
Oi 5 1 _____ 0 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11
0.12
17 01O0381 VdC 0.0364 200
19 0O.552Vdc 0.0526 . -100 J-- -- -J-----I-

23 0.O282VdC 0.0269 O - - ---4-

25 0 0
27 0 0 .23%04 0.05 0.06 0.07 0.08 0.09 0.1 0.11
0.12
29 0.0362Vdc 0.0344 20 C
TD54
31 0.0338Vdc 0.0322
33 330 0 ~~~~~~~~~~~~~~~~~~~~~~~~~>
- ,0L
-4--A---|~ ---

35 0 0 0 -
L 37 0.O75Vdc 0.0167_2t----____
39 0 0 02 0.05
4 0.06 0.07 0.08 0.09 0.1 0.12 0.11
1 Oms/div
Fig. 8 A, B, and C line to line voltage Vab, Phase voltage
Vl, and line CUrrent I. reSPeCtiVelY in CaSe Of indUCtiVe

651
V. COMPARISON BETWEEN THE PROPOSED INVERTER AND the amplitude of the harmonic components as a percentage of
THE CONVENTIONAL TWO LEVEL INVERTER the fundamental value. It is clear from the simulation and the
for the two level conventional inverter, The amplitude of the hardware results that the proposed inverter has a little harmonic
nth component of the output line to line voltage for 1800 and contents and less distorted than the conventional two level
120° are governed by the following two equations respectively inverter
equation [17]:

VQb = E -Vdccos(-)sin( aw +-) (5)

n=1,3,s,. nir 6 6 _5)
V = cos( )sin(ot+
t ) (6)
1,, flit 6 6

Based on the aforementioned discussion and from equations I

and 6 the following conclusions can be made
TABLE 11
COMPARISON BETWEEN THE PROPOSED INVERTER AND THE CONVENTIONAL
INVERTER
Fundamental Lower
THD Peak value of order
line voltage harmonic
1800 31% 1.1 027Vdc 3 Fig 9. The hardware implementation circuit
1200 31% 0.95Vdc 3
The Proposed 5
level inverter 15.5% 10487Vdc 7

From the above discussion, the following improvements have

been achieved by inserting the additional circuit which
composed of 3 switches and three diodes to the conventional > *
inverter type, they are: I>
1- The amplitude of the fundamental component of the - ' .
proposed inverter is very close to the conventional one in case I 4 I ....

of 1800.
2- The total harmonic distortion of the proposed inverter has - ) Chi. - 2 it i .*
reduced significantly (15.5% compared to 30.5%), besides the - .. .It I ins:
2) h2.5Q.nV .
lower harmonics is now the seventh as given in table II, that
means a significant reduce in the output filter.

lOms/div
EXPERIMENTAL RESULTS:
VI. Fig 1O output phase voltage of phase V,N.
In order to test the proposed inverter configuration, a
complete low power inverter was constructed as shown in Fig.
9. The experiments were conducted using open-loop controller,
because the feedback control loop and the output filter have not
been implemented yet. Besides the input dc bus voltage was
replaced by constant dc source (30 V batteries). The selected . * .
results have been chosen to illustrate the some of the main a 1>.
features of the proposed 5 level inverter. Gating signals , :
generated using Xiling XC95 108C. Simulation is carried out IJ li
using the Xilinx WebPack 4.1. So far the hardware testing is
done at low voltage and for resistive load only. Fig. 10 and 11 - : X) 1: 2 Volt O ms
show the phase output voltage and the line to line output 7)...
5Qm Y IQrmY U. J- Ms.
..:.
voltage respectively (50 volt per division). Figure 12 depicts : :_ :_:_:

lOms/div
Fig 11 output line to line voltage V.b.

652
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8.0%
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