[B! FPGA] halfrackã®ãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯

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FPGAã«é–¢ã™ã‚‹halfrackã®ãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯ (13)

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FPGA ãƒ™ãƒ¼ã‚¹ãƒ»ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢NTPã‚µãƒ¼ãƒï¼ˆStratum1ï¼‰ç‰¹è¨å®Ÿé¨“ã‚µã‚¤ãƒˆ æ¦‚è¦ ã•ãã‚‰ã‚¤ãƒ³ã‚¿ãƒ¼ãƒãƒƒãƒˆã§é–‹ç™ºã—ãŸ FPGA ãƒ™ãƒ¼ã‚¹ãƒ»ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢ NTP ã‚µãƒ¼ãƒï¼ˆStratum1ï¼‰ã®æƒ…å ±å…¬é–‹ã‚’è¡Œã£ã¦ã„ã¾ã™ã€‚ ã•ãã‚‰ã‚¤ãƒ³ã‚¿ãƒ¼ãƒãƒƒãƒˆã§ã¯ã€2020 å¹´ 3 æœˆ 17 æ—¥ã‹ã‚‰2021 å¹´ 3 æœˆ 31 æ—¥ã¾ã§ã®é–“ã€å˜ä½“ã§ç´„10ã‚®ã‚¬ãƒ“ãƒƒãƒˆï¼ç§’ï¼ˆç´„ 1300ä¸‡ ãƒªã‚¯ã‚¨ã‚¹ãƒˆï¼ç§’ï¼‰ã®é«˜è² è·ã«è€ãˆã€Stratum 1 NTP ã‚µãƒ¼ãƒãƒ¼ã¨ã—ã¦åƒãå°‚ç”¨ãƒ‡ã‚¸ã‚¿ãƒ«å›žè·¯ã‚’å†…è£½è¨è¨ˆã—ã€FPGA ä¸Šã§å‹•ä½œã•ã›ã¦æä¾›ã™ã‚‹å®Ÿé¨“ã‚’å®Ÿæ–½ã—ã¾ã—ãŸã€‚( ãƒ—ãƒ¬ã‚¹ãƒªãƒªãƒ¼ã‚¹ãƒšãƒ¼ã‚¸ ) å½“ãƒšãƒ¼ã‚¸ã§ã¯å½“æ™‚ã®å®Ÿé¨“ã®é›°å›²æ°—ã‚’ãŠä¼ãˆã™ã‚‹ã¨ã¨ã‚‚ã«ã€é–‹ç™ºã—ãŸFPGA-NTP ã‚µãƒ¼ãƒã®æŠ€è¡“æƒ…å ±ã‚’å…¬é–‹ã—ã¦ãŠã‚Šã¾ã™ã€‚ æŠ€è¡“è§£èª¬ å½“è©¦é¨“ã‚’é€šã—ã¦ç¤ºã—ãŸã„ã‚³ãƒ³ã‚»ãƒ—ãƒˆ æ˜¨ä»Šã®ãƒ‡ãƒ¼ã‚¿ã‚»ãƒ³ã‚¿ãƒ¼ã‚µãƒ¼ãƒ“ã‚¹äº‹æ¥ã«ãŠã„ã¦ã¯ã€æ—¢è£½å“ã®ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢ï¼ˆã‚µãƒ¼ãƒãƒ¼åŠã³ãƒãƒƒãƒˆãƒ¯ãƒ¼ã‚¯ã‚¹ã‚¤ãƒƒ
$halfrack$
halfrack 2020/03/17
GNSS anomaly ç™ºç”Ÿæ™‚ã®æŒ™å‹•ãŒæ°—ã«ãªã‚‹æ§‹æˆãƒ» _ga ã¤ã‘ã‚‹ãªã‚‰ canonical ã‚‚æ¬²ã—ã„ãƒ”ãƒ§ãƒ³

ntp

sakura

fpga

gnss
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$halfrack$
halfrack 2020/03/17
(æŸä½œå“ã‚ªãƒžãƒ¼ã‚¸ãƒ¥ã¨ã—ã¦)æ™‚åˆ»è¡¨ç¤ºãƒ‡ãƒã‚¤ã‚¹ã¯ãƒ‹ã‚ã‚·ãƒ¼ç®¡ãŒã„ã„ã¨ã„ã†è¨€èª¬ã‚’è¦‹ã¦æ„Ÿå‹•ã—ãŸã®ã§ãœã²ã‚„ã£ã¦ã»ã—ã„ https://twitter.com/kunukunu/status/1239792024041054208

ntp

fpga
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$halfrack$
halfrack 2018/10/05
AWS Nitro ãŸã¶ã‚“ã“ã†ã„ã†ã®ã§å®Ÿè£…ã—ã¦ã‚‹ã‚“ã ã‚ã†ãªãã¨æŽ¨æ¸¬ã—ã¦ã„ã‚‹

FPGA

hardware

virtualization

NIC

network

storage
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FPGAX9 AWS F1 instance
Amazonã®ã‚¯ãƒ©ã‚¦ãƒ‰FPGAã€F1ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ã®é–‹ç™ºç’°å¢ƒã§HellowWorldçš„ãªã‚‚ã®ã‚’ã‚„ã£ã¦ã¿ãŸã€‚
$halfrack$
halfrack 2017/09/25
AWS

FPGA
ãƒªãƒ³ã‚¯
AMD Zynqâ„¢ UltraScale+â„¢ RFSoC
Tried. Trusted. Long Lasting. With typical lifespans extending well past 15 years, you can depend on AMD devices being around for the life of your design. AMD 7 Series FPGAs and adaptive SoCs extended through 2040* AMD UltraScale+â„¢ FPGAs and adaptive SoCs extended through 2045* Read the Blog *Due to the shorter lifecycles of high-bandwidth memory (HBM) components, AMD cannot extend the lifecycle o
$halfrack$
halfrack 2017/02/23
"RFSoC" "é«˜ IF ãƒ˜ãƒ†ãƒãƒ€ã‚¤ãƒ³ãƒ¬ã‚·ãƒ¼ãƒãƒ¼ã‹ã‚‰ãƒ€ã‚¤ãƒ¬ã‚¯ãƒˆ RF ã‚µãƒ³ãƒ—ãƒªãƒ³ã‚°ãƒ¬ã‚·ãƒ¼ãƒãƒ¼ã¸"

hardware

RF

FPGA
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16nm MPSoCã«RFãƒ‡ãƒ¼ã‚¿ã‚³ãƒ³ãƒãƒ¼ã‚¿ãƒ¼ã‚’çµ±åˆ
Xilinxï¼ˆã‚¶ã‚¤ãƒªãƒ³ã‚¯ã‚¹ï¼‰ã¯ã€RFã‚¯ãƒ©ã‚¹ã®ã‚¢ãƒŠãƒã‚°æŠ€è¡“ã‚’çµ±åˆã—ãŸã€ŒAll Programmable RFSoCã€ã«ã¤ã„ã¦ã€ãã®æŠ€è¡“æ¦‚è¦ã‚’ç™ºè¡¨ã—ãŸã€‚ æ¶ˆè²»é›»åŠ›ã¨ãƒ•ãƒƒãƒˆãƒ—ãƒªãƒ³ãƒˆã€å¾“æ¥æ¯”50ï½ž75ï¼…å‰Šæ¸› Xilinxï¼ˆã‚¶ã‚¤ãƒªãƒ³ã‚¯ã‚¹ï¼‰ã¯2017å¹´2æœˆã€RFã‚¯ãƒ©ã‚¹ã®ã‚¢ãƒŠãƒã‚°æŠ€è¡“ã‚’çµ±åˆã—ãŸã€ŒAll Programmable RFSoCã€ã®è¦ç´ æŠ€è¡“ã«ã¤ã„ã¦ã€ãã®æ¦‚è¦ã‚’ç™ºè¡¨ã—ãŸã€‚5G Massive MIMOç„¡ç·šã‚·ã‚¹ãƒ†ãƒ ã‚„ãƒŸãƒªæ³¢ç„¡ç·šãƒãƒƒã‚¯ãƒ›ãƒ¼ãƒ«ã«ãŠã„ã¦ã€æ¶ˆè²»é›»åŠ›ã¨ãƒ•ãƒƒãƒˆãƒ—ãƒªãƒ³ãƒˆã‚’å¾“æ¥ã«æ¯”ã¹ã¦50ï½ž75ï¼…ã‚‚å‰Šæ¸›ã§ãã‚‹ã¨ã„ã†ã€‚ All Programmable RFSoCã¯ã€TSMCã®16nm FinFETãƒ—ãƒã‚»ã‚¹ã‚’ç”¨ã„ãŸã€ŒAll Programmable MPSoCã€ã‚’ãƒ™ãƒ¼ã‚¹ã¨ã—ã¦ã„ã‚‹ã€‚ã“ã‚Œã«ã€ã‚µãƒ³ãƒ—ãƒªãƒ³ã‚°ãƒ¬ãƒ¼ãƒˆãŒæœ€å¤§4Gã‚µãƒ³ãƒ—ãƒ«/ç§’ã§åˆ†è§£èƒ½ãŒ12ãƒ“ãƒƒãƒˆã®A-Dã‚³ãƒ³ãƒãƒ¼ã‚¿ãƒ¼ã‚„ã€åŒã˜ãæœ€å¤§6.4Gã‚µãƒ³ãƒ—ãƒ«/
$halfrack$
halfrack 2017/02/23
FPGA ã« 4GSPS è¶…ã® DAC&ADC ãŒå†…è”µã•ã‚Œã‚‹ãƒ»ãƒ€ã‚¤ãƒ¬ã‚¯ãƒˆã‚µãƒ³ãƒ—ãƒªãƒ³ã‚°ã—æ”¾é¡Œ

FPGA

hardware

RF
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FPGAã®åŽŸç†ã¨æ§‹æˆã‚’èªã‚“ã - xiangze's sparse blog
FPGAãƒ–ãƒ¼ãƒ ãŒæ¥ã¦ã„ã¾ã™*1 ã€‚ æœ€è¿‘å¹´ã‚’è¿½ã†ã”ã¨ã«FPGAã«é–¢ã™ã‚‹æ›¸ç±ã‚„ãƒãƒƒãƒˆä¸Šã®æƒ…å ±ãŒå¤šããªã‚Šã€ã¾ãŸCè¨€èªžãƒ™ãƒ¼ã‚¹ã§ã®é«˜ä½åˆæˆæŠ€è¡“ã®é€²å±•ã‚„Linuxãƒ™ãƒ¼ã‚¹ã®ã‚·ã‚¹ãƒ†ãƒ ãŒä½œã‚‰ã‚Œã€FPGAã¯ã‚½ãƒ•ãƒˆã‚¦ã‚§ã‚¢é–‹ç™ºè€…ã«ã¨ã£ã¦ã®æ•·å±…ãŒä½Žãä½¿ã„ã‚„ã™ããªã£ã¦ãã¦ã„ã¾ã™ã€‚ã—ã‹ã—å…¥æ‰‹ã§ãã‚‹æƒ…å ±ã¯ç‰¹å®šã®ãƒ™ãƒ³ãƒ€ãƒ¼ã®è£½å“ã€ãƒ„ãƒ¼ãƒ«ã®ä½¿ç”¨ã‚’æƒ³å®šã—ãŸå®Ÿè·µçš„ãªã‚‚ã®ãŒå¤šãã€ä¸ç«‹çš„ç«‹å ´ã‹ã‚‰FPGAã®å†…éƒ¨æ§‹æˆã‚„å‹•ä½œã™ã‚‹åŽŸç†ã«ã¤ã„ã¦è§£èª¬ã—ãŸæ—¥æœ¬èªžã®æœ¬ã¯ã»ã¨ã‚“ã©è¦‹å½“ãŸã‚Šã¾ã›ã‚“ã§ã—ãŸã€‚ ã€ŒFPGAã®åŽŸç†ã¨æ§‹æˆã€ã¯ãã®ã‚ˆã†ãªæ„å‘³ã§ä»–ã«ã¯ãªã„ã€ã“ã®æœ¬ã«ã—ã‹è¼‰ã£ã¦ã„ãªã„äº‹æŸ„ã®å¤šã„æœ¬ã«ãªã£ã¦ã„ã¾ã™ã€‚ FPGAã®åŽŸç†ã¨æ§‹æˆ shop.ohmsha.co.jp 1ç« FPGAã‚’ç†è§£ã™ã‚‹ãŸã‚ã®åŸºæœ¬äº‹é … 2ç« FPGAã®æ¦‚è¦ 3ç« FPGAã®æ§‹æˆ 4ç« è¨è¨ˆãƒ•ãƒãƒ¼ã¨ãƒ„ãƒ¼ãƒ« 5ç« è¨è¨ˆæŠ€è¡“ 6ç« ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢ã‚¢ãƒ«ã‚´ãƒªã‚ºãƒ 7ç« PLD/FPGAã®å¿œç”¨äº‹
$halfrack$
halfrack 2017/01/04
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hardware

FPGA
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ãã‚ãã‚ãƒ—ãƒã‚°ãƒ©ãƒžãƒ¼ã‚‚FPGAã‚’è§¦ã£ã¦ã¿ã‚ˆã†ï¼ - Qiita
##ãã‚ãã‚ãƒ—ãƒã‚°ãƒ©ãƒžãƒ¼ã‚‚FPGAã‚’è§¦ã£ã¦ã¿ã‚ˆã†ï¼ ã“ã‚Œã¯builderscon tokyo 2016ã®ç™ºè¡¨ã‚¹ãƒ©ã‚¤ãƒ‰ã§ã™ã€‚ ##è‡ªå·±ç´¹ä»‹ @kazunori_279 ã‚¯ãƒ©ã‚¦ãƒ‰ã®ãƒ‡ãƒ™ãƒãƒƒãƒ‘ãƒ¼ãƒ»ã‚¢ãƒ‰ãƒœã‚±ã‚¤ãƒˆ ã‚¨ãƒãƒ³ã‚¸ã‚§ãƒªã‚¹ãƒˆã¿ãŸã„ãªãŠä»•äº‹ ã‚³ãƒŸãƒ¥ãƒ‹ãƒ†ã‚£æ”¯æ´ï¼šGCPUGã€bq_sushiã€TensorFlow User Group etc è¶£å‘³ã®FPGA 2013å¹´ãã‚‰ã„ã‹ã‚‰ã„ã˜ã‚Šå§‹ã‚ FPGAã‚¨ã‚¯ã‚¹ãƒˆãƒªãƒ¼ãƒ ãƒ»ã‚³ãƒ³ãƒ”ãƒ¥ãƒ¼ãƒ†ã‚£ãƒ³ã‚°ä¸»å®°ï¼šåˆè¨ˆ8å›ž ##ã“ã‚Œã¾ã§ã«æ›¸ã„ãŸFPGAè¨˜äº‹ ã¯ã¦ãªãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯ã§ãƒã‚ºã£ãŸè¨˜äº‹ãŸã¡ ãƒžã‚¤ã‚¯ãƒã‚½ãƒ•ãƒˆã¯ã©ã†ã‚„ã£ã¦Bingã‚’FPGAã§å®Ÿè£…ã—ãŸã‹: 952 users ãƒãƒ¼ãƒ‰ç´ äººãŒ32bit CPUã‚’FPGAã§è‡ªä½œã—ã¦å‹•ã‹ã™ã¾ã§èªã‚“ã æœ¬ã®ã¾ã¨ã‚: 576 users æ–‡å—é€šã‚Šã€Œãƒãƒƒãƒˆãƒ¯ãƒ¼ã‚¯ãŒã‚³ãƒ³ãƒ”ãƒ¥ãƒ¼ã‚¿ãƒ¼ã€ãªé‡‘èžHFTã§ã®FPGAã®ä½¿ã‚ã‚Œæ–¹: 517 users JP M
$halfrack$
halfrack 2016/12/03
FPGA
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ï¼»é€Ÿå ±ï¼½AWSã€FPGAã‚’åˆ©ç”¨å¯èƒ½ãªã€ŒF1 Instancesã€ã‚’ç™ºè¡¨ã€‚ã‚¯ãƒ©ã‚¦ãƒ‰ã§ãƒ—ãƒã‚°ãƒ©ãƒžãƒ–ãƒ«ãªãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢ã‚¢ã‚¯ã‚»ãƒ©ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã‚’å®Ÿç¾å¯èƒ½ã«ã€‚AWS re:Invent 2016
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halfrack 2016/12/01
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FPGA

AWS
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Homemade GPS Receiver
Pictured above is the front-end, first mixer and IF amplifier of an experimental GPS receiver. The leftmost SMA is connected to a commercial antenna with integral LNA and SAW filter. A synthesized first local oscillator drives the bottom SMA. Pin headers to the right are power input and IF output. The latter is connected to a Xilinx FPGA which not only performs DSP, but also hosts a fractional-N f
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halfrack 2016/11/20
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RF

FPGA

GPS
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Intelã€Alteraã®FPGAã€ŒArria 10 GXã€ã‚’1ãƒ‘ãƒƒã‚±ãƒ¼ã‚¸ã«çµ±åˆã—ãŸXeon
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halfrack 2016/04/08
Altera Stratix V ãŒ QPI ã§æŽ¥ç¶šï¼ï¼

hardware

CPU

FPGA
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halfrack 2014/02/20
FPGA
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Under Construction advancedio.com
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halfrack 2012/03/27
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network

FPGA
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