VHDL 2008/93/87 simulator

SPI master and SPI slave for FPGA written in VHDL

Simple UART controller for FPGA written in VHDL

A JSON library implemented in VHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Trying to verify Verilog/VHDL designs with formal methods and tools

cryptography ip-cores in vhdl / verilog

Virtual development board for HDL design

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

Library of reusable VHDL components

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Experiments with Cologne Chip's GateMate FPGA architecture

Custom 64-bit pipelined RISC processor

Simple VHDL examples using ghdl as compiler and wave generating

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

Remote control in VHDL, which fits on a Lattice icestick.

Collection of generic VHDL modules

Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

Professional VHDL Class Solution - StopWatch