High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Test bench to measure and investigate performance of Apache Maven project

LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.

VLSI System Design Practice Lab

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

Hosting all of my ZeroBraine Lua projects

A project to design a test-bench for thermal and pressure conditions in which a CubeSat satellite is subjected in space.

Simple equalization circuit specified using VHDL

VHDL assignments done at @ufms.

Test bench to develop a 16b fixed point PID class for OrangeBot

Design and manufacture a mechanical testing bench for mechanical vibration of CubeSat satellites from 1U to 3U, according to NASA-GEVS standard: GSFC-STD-7000A.

Circuito combinacional con entrada de 4 bits (número sin signo en binario puro) y salida con un número de 4 bits, su valor es redondear la operación 4 x RAIZ CUADRADA(y) al entero más próximo. El circuito se diseña de diversas maneras, cada una con una descripción en VHDL como arquitectura de la entidad.

A VHDL implementation of Finite State Machines (FSM) and reverse engineering other hidden FSMs

Design of a control algorithm for a testing bench of sinusoidal, random and shock mechanical vibrations for CubeSats from 1U to 3U.

Project to design a test platform to suspend a satellite, for recreating the low-friction conditions they are subjected in space and to test ADCS performance of CubeSat.

Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.

Design and build a PCB shield including a low-tech graphite strain sensor coupled to an analog electronic circuit that communicate data via a microcontroller to an Android application

📋 List of practical and laboratory works from Hardware&Software Development subject from university