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functional-coverage

Here are 7 public repositories matching this topic...

chiselverify / chiselverify

A dynamic verification library for Chisel.

testing coverage scala verification chisel constrained-random-verification functional-coverage bus-functional-model chisel-test timed-assertions

Updated Nov 9, 2024
Scala

fvutils / pyvsc

Python packages providing a library for Verification Stimulus and Coverage

python coverage randomization constraints constrained-random cocotb verification-stimulus random-stimulus functional-coverage

Updated Sep 22, 2024
Python

tmeissner / psl_with_ghdl

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Jan 30, 2023
VHDL

fvutils / pyucis

Python API to Unified Coverage Interoperability Standard (UCIS) Data

functional-coverage ucis accellera-ucis coverage-database

Updated Sep 28, 2024
Python

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design

Updated Jun 26, 2024
Verilog

Vivek-Dave / UVM_TestBench_For_S_R_Latch

Simple and Complete UVM TestBench For Verification Of S R Latch

verification uvm functional-coverage

Updated Jun 19, 2021
SystemVerilog

Vivek-Dave / UVM_TestBench_For_Ring_Counter

Complete UVM TestBench For Verification Of Ring (Onehot) Counter

uvm functional-coverage

Updated Jun 19, 2021
SystemVerilog

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