Verilator open-source SystemVerilog simulator and lint system
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Nov 24, 2024 - C++
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verilator
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A small, light weight, RISC CPU soft core
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Oct 15, 2024 - Verilog
RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
32-bit Superscalar RISC-V CPU
linux
asic
cpu
fpga
verilog
xilinx
superscalar
in-order
risc-v
branch-prediction
coremark
rv32i
verilator
riscv-linux
rv32im
artix-7
pipelined-processors
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Sep 18, 2021 - Verilog
VeeR EH1 core
fpga
processor
riscv
rtl
risc
risc-v
open-source-hardware
fusesoc
verilator
riscv32
western-digital
axi4
ahb-lite
asic-design
veer
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May 29, 2023 - SystemVerilog
An abstraction library for interfacing EDA tools
fpga
simulation
vhdl
eda
verilog
xilinx
synthesis
vivado
altera
systemverilog
icestorm
lattice
icarus-verilog
modelsim
ghdl
yosys
verilator
riviera-pro
fossi
spyglass
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Nov 22, 2024 - Python
HDL support for VS Code
ctags
vscode
verilog
vivado
systemverilog
icarus-verilog
modelsim
hacktoberfest
verilog-hdl
iverilog
bluespec-systemverilog
verilator
language-server-client
systemverilog-support
svls
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Nov 22, 2024 - TypeScript
A simple, basic, formally verified UART controller
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Jan 29, 2024 - Verilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
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Nov 25, 2019 - SystemVerilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic
fpga
async
verification
verilog
synthesis
icarus-verilog
fifo
cdc
hdl
verilog-hdl
fifo-queue
fifo-cache
verilator
asic-design
cross-clock-domain
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Apr 30, 2024 - Verilog
VeeR EL2 Core
fpga
processor
riscv
rtl
risc-v
open-source-hardware
fusesoc
verilator
riscv32
western-digital
axi4
ahb-lite
asic-design
el2
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Nov 22, 2024 - SystemVerilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface
fpga
verilog
sd-card
sdio
wishbone
verilog-components
verilator
axi
emmc
wishbone-bus
sd-interface
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Nov 12, 2024 - Verilog
A utility for Composing FPGA designs from Peripherals
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Jan 18, 2024 - C++
A wishbone controlled scope for FPGA's
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Jan 12, 2024 - Verilog
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
python
flow
simulator
tdd
simulation
foss
verilog
testcase
tdd-utilities
mit-license
systemverilog
icarus-verilog
gtkwave
verification-methodologies
vcd
verilator
surfer
svut
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Oct 22, 2024 - Python
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