#

vivado-simulator

Here are 13 public repositories matching this topic...

suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

Updated Jun 6, 2024
Python

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

wyvernSemi / mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

Updated Nov 20, 2024
VHDL

esynr3z / pyhdlsim

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

mzh330521 / SublimeLinter-contrib-xsim

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

sublime-text vhdl sublimelinter linter-plugin verilog systemverilog xsim vivado-simulator

Updated May 29, 2024
Python

RipperJ / VerilogExpr2NAND-NOR

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

compiler simulation lex espresso ply verilog yacc boolean-expression nand logic-minimization nor xsim vivado-simulator pyeda

Updated Jun 4, 2023
Python

Ammar-Bin-Amir / SystemVerilog_Practice

Practice Codes of SystemVerilog Language

vscode systemverilog vivado-simulator

Updated May 19, 2024
SystemVerilog

arhamhashmi01 / Axi4-lite

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface

Updated May 4, 2024
SystemVerilog

amirah-sri / all_verilog

I am trying to develop my skills through daily practice and consistency.

verilog vivado vlsi verilog-hdl verilog-programs verilog-project verilog-code vivado-simulator

Updated Jul 31, 2024
Verilog

WimukthiMadushan / Computer-Organization-and-Digital-Design

Includes lab exercises from my Computer Organization and Digital Design module. It features implementations of various components inside a processor using VHDL . Finally I make 4 bit nanoprocessor combining all components those build in previous labs.

vhdl vivado vhdl-code vivado-simulator nanoprocessor

Updated Jan 25, 2024
VHDL

rishz09 / digital-safe-verilog

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

verilog vivado digital-design verilog-project pynq-z2 vivado-simulator digital-safe

Updated Jul 1, 2024
Tcl

anr2311 / I2C_State_Machine

This repo contains an I2C transaction state machine modelled in Verilog targeted for the Zynq Zedboard

i2c-bus vivado-simulator

Updated Nov 23, 2024
Verilog

Imtjl / digital-design-fundamentals

Digital design fundamentals - a 3rd year CSE banchelor course in ITMO University

circuits system-verilog verilog-hdl digital-design spice-simulator vivado-simulator system-verification

Updated Nov 22, 2024
TeX

Improve this page

Add a description, image, and links to the vivado-simulator topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the vivado-simulator topic, visit your repo's landing page and select "manage topics."