Merge pull request #563 from aws/REL_4_24_kyyalama

Updates to documentation for migration between F1 and U200 in vivado flow

Merge pull request #547 from aws/REL_v1_4_23

Enable 2021.2

Release v1.4.22 (#540)

* Updated README.md and FAQ.md: (#702)

* Added descriptions on kernel clocks and frequency scaling.

* Virtual Ethernet upgrade (#694)

* Update dpdk to v20.02 for virtual eth instance and dpdk to v20.08 and pktgen to v20.09 for pktgen instance

* update to include a dpdk patch for generating igb

* update the script to also generate igb_uio.ko for x86_64-native-linuxapp-gcc

* updated dpdk patches for 20.02

* updates to spp_ethdev.c

* remove spp_ethdev.c as its updated in 0001 patch

* update the patch to enable igb_uio compilation

* updates to virtual_ethernet_install.py for upgrade to 20.02

* Update Virtual_Ethernet_Application_Guide.md

* Updated the end of life announcement table (#703)

Co-authored-by: czfpga <[email protected]>
Co-authored-by: kyyalama2 <[email protected]>

Release v1.4.21 (#528)

* Enable Xilinx 2021.1 tools
* Update DCV instructions to 2021.1

Updated version support to add variations of patches

Up-rev hdk version and add Release notes (#526)

Release v1.4.19 (#515)

* Bug Fix release to fix CDC path in flop_ccf.sv
* Updated Errata with details

Release v1.4.18 (#514)

* Fixed the broken links pointing to the AXI interface specifications

* Enable Xilinx 2020.2 tools

* Updated FAQ on how to request an AFI limit increase

Release v1.4.17 (#505)

* Updated XDMA Driver to allow builds on newer kernels
* Updated documentation on Alveo U200 to F1 platform porting
* Added Vitis 2019.2 Patching for AR#73068

Release v1.4.16 (#502)

* FPGA developer kit now supports Xilinx Vivado/Vitis 2020.1
* Updated Vitis examples to include usage of Vitis Libraries.
* Added documentation and examples to show Xilinx Alveo design migration to F1.
* Removed support for Xilinx toolsets 2017.4, 2018.2 and 2018.3.