Release v1.4.17 (#505)

* Updated XDMA Driver to allow builds on newer kernels * Updated documentation on Alveo U200 to F1 platform porting * Added Vitis 2019.2 Patching for AR#73068
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diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -1,5 +1,10 @@
 # AWS EC2 FPGA HDK+SDK Release Notes
 
+## Release 1.4.17 (See [ERRATA](./ERRATA.md) for unsupported features)
+* Updated XDMA Driver to allow builds on newer kernels
+* Updated documentation on Alveo U200 to F1 platform porting
+* Added Vitis 2019.2 Patching for AR#73068
+
 ## Release 1.4.16 (See [ERRATA](./ERRATA.md) for unsupported features)
 * FPGA developer kit now supports Xilinx Vivado/Vitis 2020.1
     * To upgrade, use [Developer AMI v1.9.0](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) on the AWS Marketplace.

diff --git a/Vitis/docs/Alveo_to_AWS_F1_Migration.md b/Vitis/docs/Alveo_to_AWS_F1_Migration.md
@@ -161,67 +161,6 @@ A detailed working example walking through all the steps required to migrate an
 In this example, the source code for the software program and the FPGA kernels remains identical whether targeting U200 or F1 instances. 
 Only command line changes are necessary to port the application. 
 
-The Vitis flow leverages dedicated compilation steps to build the software program and FPGA accelerators. These steps are described below.
-
-
-
-### Compiling the software program
-
-The software program is compiled exactly in the same way in both case:
-
-```bash
-g++ -D__USE_XOPEN2K8 -I/$(XILINX_XRT)/include/ -I./src -O3 -Wall -fmessage-length=0 -std=c++11 ../src/host.cpp -L/$(XILINX_XRT)/lib/ -lxilinxopencl -lpthread -lrt -o host
-```
-
-The software program is linked with the XRT libraries which manages the specific requirements of each FPGA platform, allowing the source code to remain the same for U200 and F1.
-
-See [here](https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/buildinghostprogram.html#asy1528754332783) for more details about building the host program for the Vitis flow.
-
-
-### Compiling the FPGA binary
-
-When building the FPGA binary only a few options need to be changed when retargeting from U200 and F1 instances. These options are contained in a specific file (called options.cfg in our example) and which is passed to the Vitis v++ compiler with the `--config` command line option. 
-
-Here is a side-by-side view of the both options.cfg files:
-
-| Contents of options.cfg for Alveo U200                       | Contents of options.cfg for AWS F1                           |
-| ------------------------------------------------------------ | ------------------------------------------------------------ |
-| platform=xilinx_u200_xdma_201830_2<br />[connectivity] <br />sp=vadd_1.in1:DDR[1] <br />sp=vadd_1.in2:DDR[1]  <br />sp=vadd_1.out:DDR[1] | platform=xilinx_aws-vu9p-f1_shell-v04261818_201920_2<br />[connectivity]  <br />sp=vadd_1.in1:DDR[0]  <br />sp=vadd_1.in2:DDR[0]  <br />sp=vadd_1.out:DDR[0] |
-
-The platform option specifies which acceleration platform is targeted for the build. 
-
-The `sp` option is used to specify the assignment of kernel interfaces to DDR interfaces. The original U200 design is connecting the kernel interfaces to DDR[1] which is located in the shell. Keeping the same settings would produce a working design on F1 instances, but in order to produce exactly the same configuration and target the DDR interface located in the F1 shell, the `sp` options are modified to use DDR[0].
-
-Putting all the platform specific options in a dedicated file allows the v++ build commands remain strictly identical:
-
-```bash
-// Step 1: compile the kernel from source code
-v++ -c -g -t hw -R 1 -k vadd --profile_kernel data:all:all:all --profile_kernel stall:all:all:all --save-temps --temp_dir ./temp_dir --report_dir ./report_dir --log_dir ./log_dir --config ./options.cfg -I../src ../src/vadd.cpp -o ./vadd.hw.xo
-
-// Step 2: link the compiled kernel with the shell and produce the FPGA binary
-v++ -l -g -t hw -R 1 --profile_kernel data:all:all:all --profile_kernel stall:all:all:all --temp_dir ./temp_dir --report_dir ./report_dir --log_dir ./log_dir --config ./options.cfg -I../src vadd.hw.xo -o add.hw.xclbin
-```
-
-See [here](https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/vitiscommandcompiler.html#wrj1504034328013) for more information about the v++ command line options and configuration files.
-
-
-
-### Creating the Amazon FPGA Image
-
-Once you have compiled the host program and the FPGA binary, you are ready to execute the FPGA-accelerated application on a server equipped with an Alveo U200 acceleration card.
-
-When targeting  F1 instances, you need to go through the additional step of creating an Amazon FPGA Image (AFI). This is done with the `create_vitis_afi.sh` command provided by AWS. This command reads in the FPGA binary generated by the v++ linker and requires information about the user’s AWS S3 bucket.
-
-In this example, the command looks as follows:
-
-```bash
-$AWS_FPGA_REPO_DIR/Vitis/tools/create_vitis_afi.sh -xclbin=./vadd.xclbin -o=./vadd -s3_bucket=<bucket-name> -s3_dcp_key=f1-dcp-folder -s3_logs_key=f1-logs
-```
-
-For more details about the `create_vitis_afi.sh` command, you can consult the AWS documentation [here](https://github.com/aws/aws-fpga/blob/master/Vitis/README.md#2-create-an-amazon-fpga-image-afi).
-
-
-
 ## Summary – Migration Checklist
 
 Because Vitis provides platform-independent APIs and interfaces to the developer, the process of migrating applications across similar FPGA acceleration cards is greatly facilitated.

diff --git a/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md b/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md
@@ -7,18 +7,18 @@ The Vitis development flow provides platform independent APIs and interfaces to
 
 ## Example Overview  
 
-The accelerator used in this example is a simple vector-add kernel. The `src` directory contains the source code for the project:
+The accelerator used in this example is a simple vector-add kernel. The [`src`](./src) directory contains the source code for the project:
 
-- `vadd.cpp` contains the C++ source code of the accelerator which adds 2 arbitrarily sized input vectors. 
-- `host.cpp` contains the main function running on the host CPU. The host application is written in C++ and uses OpenCL™ APIs to interact with the FPGA accelerator.
+- [`vadd.cpp`](./src/vadd.cpp)  contains the C++ source code of the accelerator which adds 2 arbitrarily sized input vectors. 
+- [`host.cpp`](./src/host.cpp) contains the main function running on the host CPU. The host application is written in C++ and uses OpenCL™ APIs to interact with the FPGA accelerator.
 
-The `u200` and `f1` directories contain the Makefiles and scripts for building for Alveo U200 and AWS F1 respectively.
+The [`u200`](./u200) and  The [`u200`](./u200) and [`f1`](./f1) directories contain the Makefiles and scripts for building for Alveo U200 and AWS F1 respectively.  directories contain the Makefiles and scripts for building for Alveo U200 and AWS F1 respectively.
 
 
 
 ## Building for Alveo U200
 
-*Note: The instructions below assume that the required tools and platforms are installed and that the environment is properly setup to run Vitis.*
+*Note: The instructions below assume that the required tools and platforms are installed and that the environment is properly setup to run Vitis. It is also a good idea to complete the Vitis example flow end-to-end before running this example.*
 
 1. Go to the `u200` directory 
 

diff --git a/Vitis/tests/test_build_vitis_example.py b/Vitis/tests/test_build_vitis_example.py
@@ -103,7 +103,7 @@ def base_test(self, examplePath, target, rteName, xilinxVersion, clean=True, che
         if check:
             check_string = "check"
 
-        (rc, stdout_lines, stderr_lines) = self.run_cmd("make {0} TARGET={1} DEVICE={2} all".format(check_string, target, os.environ['AWS_PLATFORM']))
+        (rc, stdout_lines, stderr_lines) = self.run_cmd("make {0} TARGET={1} DEVICE={2} all PROFILE=yes".format(check_string, target, os.environ['AWS_PLATFORM']))
         assert rc == 0, "Vitis build failed with rc={}".format(rc)
 
         # Check for non zero xclbin

diff --git a/hdk/hdk_version.txt b/hdk/hdk_version.txt
@@ -1 +1 @@
-HDK_VERSION=1.4.16
+HDK_VERSION=1.4.17
diff --git a/shared/bin/set_common_functions.sh b/shared/bin/set_common_functions.sh
@@ -69,8 +69,7 @@ function get_base_vivado_version {
         local MYVIVADO_ENV_VAR_BACKUP=$MYVIVADO
 
         unset MYVIVADO
-        local __vivado_version=$(get_vivado_v
-        ersion)
+        local __vivado_version=$(get_vivado_version)
         export MYVIVADO=$MYVIVADO_ENV_VAR_BACKUP
     elif is_xilinx_path_set
     then
@@ -116,8 +115,9 @@ function get_vivado_version {
 }
 
 function setup_patches {
+    local caller_script="${BASH_SOURCE[1]}"
     patch_AR71715
-    patch_AR73068
+    patch_AR73068 "$caller_script"
 }
 
 function is_patch_applied {
@@ -211,13 +211,28 @@ function install_patch {
     fi
 }
 
-function patch_AR73068_2019_2 {
-    info_msg "Patching Vivado 2019.2 with Xilinx Patch AR73068"
+function fix_patch_vitis_AR73068_2019_2 {
+    local patch_object="$1"
+    local patch_dir_name="${patch_object%.*}"
+    pushd patches/$patch_dir_name
+
+    sed -i '/.*checksum.*/d' ./vivado/data/ip/xilinx/ddr4_v2_2/component.xml
+    sed -i 's/coreRevision>73068/coreRevision>8/' ./vivado/data/ip/xilinx/ddr4_v2_2/component.xml
+    popd
+}
 
+function patch_AR73068_2019_2 {
+    info_msg "Patching Vivado/Vitis 2019.2 with Xilinx Patch AR73068"
+    local fix_patch="$1"
     local patch_bucket="https://aws-fpga-developer-ami.s3.amazonaws.com/1.8.0/Patches/AR73068"
     local patch_object="AR73068_Vivado_2019_2_preliminary_rev1.zip"
 
     install_patch "AR73068" "$patch_bucket" "$patch_object"
+
+    if [[ "$fix_patch" == true ]]; then
+      info_msg "Fixing Patch AR73068 for Vitis"
+      fix_patch_vitis_AR73068_2019_2 "$patch_object"
+    fi
 }
 
 function patch_AR73068_2019_1 {
@@ -258,9 +273,17 @@ function patch_AR73068_2017_4 {
 
 function patch_AR73068 {
     local base_vivado_version=$(get_base_vivado_version)
+    local caller_script="$1"
+    local fix_patch=false
+
+    # Vitis specific changes
+    if [[ "$caller_script" =~ "vitis_setup.sh" ]]; then
+      info_msg "Patching Vitis with AR73068"
+      fix_patch=true
+    fi
 
     if [[ "${base_vivado_version}" =~ "Vivado v2019.2" ]]; then
-      patch_AR73068_2019_2
+      patch_AR73068_2019_2 "$fix_patch"
     elif [[ "${base_vivado_version}" =~ "Vivado v2019.1" ]]; then
       patch_AR73068_2019_1
     elif [[ "${base_vivado_version}" =~ "Vivado v2018.3" ]]; then

diff --git a/vitis_setup.sh b/vitis_setup.sh
@@ -165,8 +165,8 @@ fi
 
 info_msg " XILINX_VITIS is set to $XILINX_VITIS"
 # Install patches as required.
-#info_msg " Checking & installing required patches"
-#setup_patches
+info_msg " Checking & installing required patches"
+setup_patches
 
 
 # Update Xilinx Vitis Examples from GitHub