Release v1.4.18 (#514)

* Fixed the broken links pointing to the AXI interface specifications * Enable Xilinx 2020.2 tools * Updated FAQ on how to request an AFI limit increase
aws · Mar 18, 2021 · 4750aac · 4750aac
1 parent aeda393
commit 4750aac
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diff --git a/.gitmodules b/.gitmodules
@@ -8,3 +8,6 @@
 [submodule "Vitis/examples/xilinx_2020.1"]
 	path = Vitis/examples/xilinx_2020.1
 	url = https://github.com/Xilinx/Vitis_Accel_Examples
+[submodule "Vitis/examples/xilinx_2020.2"]
+	path = Vitis/examples/xilinx_2020.2
+	url = https://github.com/Xilinx/Vitis_Accel_Examples
diff --git a/FAQs.md b/FAQs.md
@@ -103,7 +103,15 @@ Every FPGA deployed in AWS cloud includes an AWS Shell, and the developer Custom
 
 It is the compiled FPGA code that is loaded into an FPGA in AWS for performing the Custom Logic (CL) function created by the developer. AFIs are maintained by AWS according and associated with the AWS account that created them. The AFI includes the CL and AWS FPGA Shell. An AFI ID is used to reference a particular AFI from an F1 instance.
 
-The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 100 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed.
+The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 500 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed.
+
+**Q: How do I increase my AFI limit?**
+
+You can increase your AFI limit by creating an [AWS Support Case](https://console.aws.amazon.com/support/home#/case/create). 
+1. Select the `Service Limit Increase` tab 
+2. In the `Limit Type`, select `EC2 FPGA`
+3. Select the region(s) where you want your limit to be increased
+4. Add justification for the limit increase. 
 
 
 **Q: What regions are supported?**

diff --git a/Jenkinsfile b/Jenkinsfile
@@ -126,9 +126,9 @@ task_label = [
 ]
 
 // Put the latest version last
-def xilinx_versions = [ '2019.1', '2019.2', '2020.1' ]
+def xilinx_versions = [ '2019.1', '2019.2', '2020.1' , '2020.2' ]
 
-def vitis_versions = ['2019.2', '2020.1']
+def vitis_versions = ['2019.2', '2020.1' , '2020.2' ]
 
 // We want the default to be the latest.
 def default_xilinx_version = xilinx_versions.last()
@@ -139,7 +139,8 @@ def dsa_map = [
 
 def xsa_map = [
     '2019.2' : [ 'DYNAMIC':'dyn'],
-    '2020.1' : [ 'DYNAMIC':'dyn']
+    '2020.1' : [ 'DYNAMIC':'dyn'],
+    '2020.2' : [ 'DYNAMIC':'dyn']
 ]
 
 def sdaccel_example_default_map = [
@@ -165,6 +166,14 @@ def vitis_example_default_map = [
         'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
         'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm',
         'gzip_app': 'Vitis/examples/xilinx/library_examples/gzip_app'
+    ],
+    '2020.2' : [
+        'Hello_World_1ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_helloworld',
+        'Gmem_2Banks_2ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_gmem_2banks',
+        'Kernel_Global_Bw_4ddr': 'Vitis/examples/xilinx/cpp_kernels/kernel_global_bandwidth',
+        'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
+        'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm',
+        'gzip_app': 'Vitis/examples/xilinx/library_examples/gzip_app'
     ]
 ]
 
@@ -186,6 +195,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
          'questa': 'questa/2019.4',
          'ies': 'incisive/15.20.079'
+     ],
+     '2020.2' : [
+         'vivado': 'xilinx/Vivado/2020.2',
+         'vcs': 'synopsys/vcs-mx/Q-2020.03',
+         'questa': 'questa/2020.2',
+         'ies': 'incisive/15.20.083'
      ]
 ]
 

diff --git a/Jenkinsfile_int_sims b/Jenkinsfile_int_sims
@@ -36,7 +36,7 @@ task_label = [
 ]
 
 // Put the latest version last
-def xilinx_versions = [ '2019.2' ]
+def xilinx_versions = [ '2020.2' ]
 
 // We want the default to be the latest.
 def default_xilinx_version = xilinx_versions.last()
@@ -53,6 +53,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
          'questa': 'questa/2019.4',
          'ies': 'incisive/15.20.079'
+     ],
+     '2020.2' : [
+         'vivado': 'xilinx/Vivado/2020.2',
+         'vcs': 'synopsys/vcs/Q-2020.03',
+         'questa': 'questa/2019.4_3',
+         'ies': 'incisive/15.20.083'
      ]
 ]
 
@@ -177,7 +183,7 @@ if (test_sims) {
                                         module purge
                                         module load python/3.7.2
                                         module load python/2.7.14
-                                        module load batch
+                                        module load slurm
                                         module load ${vivado_module}
                                         module load ${vcs_module}
                                         module load ${questa_module}

diff --git a/README.md b/README.md
@@ -50,6 +50,7 @@ AWS marketplace offers multiple versions of the FPGA Developer AMI. The followin
 
 | Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version |
 |-----------|-----------|------|
+| 1.4.18+ | 2020.2 | v1.10.X (Xilinx Vivado/Vitis 2020.2) |
 | 1.4.16+ | 2020.1 | v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1) |
 | 1.4.13+ | 2019.2 | v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2) |
 | 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) |

diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -1,5 +1,8 @@
 # AWS EC2 FPGA HDK+SDK Release Notes
 
+## Release 1.4.18 (See [ERRATA](./ERRATA.md) for unsupported features)
+* FPGA developer kit now supports Xilinx Vivado/Vitis 2020.2
+
 ## Release 1.4.17 (See [ERRATA](./ERRATA.md) for unsupported features)
 * Updated XDMA Driver to allow builds on newer kernels
 * Updated documentation on Alveo U200 to F1 platform porting

diff --git a/Vitis/docs/Create_Runtime_AMI.md b/Vitis/docs/Create_Runtime_AMI.md
@@ -4,8 +4,9 @@
 
 | Vitis Version used for AFI Development | Compatible Xilinx Runtime |
 |--------------------------------------|-----------------------------|
-| 2020.1 | AWS FPGA Developer AMI 1.9.0 (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html) |
-| 2019.2 | AWS FPGA Developer AMI 1.8.0 (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html) |
+| 2020.2 | AWS FPGA Developer AMI 1.10.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.2/html/build.html) |
+| 2020.1 | AWS FPGA Developer AMI 1.9.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html) |
+| 2019.2 | AWS FPGA Developer AMI 1.8.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html) |
 
 ## 1. Launch a Runtime Instance & Install Required Packages 
 

diff --git a/Vitis/docs/XRT_installation_instructions.md b/Vitis/docs/XRT_installation_instructions.md
@@ -4,8 +4,9 @@
 * We provide pre-built RPM's for Centos/RHEL/AL2 and instructions for building XRT 
 * Use the below table as reference to install and use the correct XRT version for your applications.
 
-| Xilinx Vitis Tool Version | XRT Release Tag | SHA | `xrt`|`xrt-aws` RPM's (Centos/RHEL) |`xrt`|`xrt-aws` RPM's (AL2) 
-|---|---|---|---|
+| Xilinx Vitis Tool Version | XRT Release Tag | SHA | `xrt` or `xrt-aws` RPM's (Centos/RHEL) |`xrt` or`xrt-aws` RPM's (AL2) |
+|---|---|---|---|---|
+|2020.2| [202020.2.8.743](https://github.com/Xilinx/XRT/releases/tag/202020.2.8.743) | 77d5484b5c4daa691a7f78235053fb036829b1e9 | [xrt_202020.2.8.0_7.9.2009-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_7.9.2009-x86_64-xrt.rpm) [xrt_202020.2.8.0_7.9.2009-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_7.9.2009-x86_64-aws.rpm) | [xrt_202020.2.8.0_2-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_2-x86_64-xrt.rpm) [xrt_202020.2.8.0_2-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_2-x86_64-aws.rpm)|
 |2020.1| [202010.2.6.AWS](https://github.com/Xilinx/XRT/releases/tag/202010.2.6.AWS) | d09c4a458c16e8d843b3165dcf929c38f7a32b6f | [xrt_202010.2.6.0_7.7.1908-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_7.7.1908-x86_64-xrt.rpm) [xrt_202010.2.6.0_7.7.1908-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_7.7.1908-x86_64-aws.rpm) | [xrt_202010.2.6.0_2-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_2-x86_64-xrt.rpm) [xrt_202010.2.6.0_2-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_2-x86_64-aws.rpm)|
 |2019.2| [2019.2.0.3](https://github.com/Xilinx/XRT/releases/tag/2019.2.0.3) | 9e13d57c4563e2c19bf5f518993f6e5a8dadc18a | [xrt_201920.2.3.0_7.7.1908-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.8.0/Patches/XRT_2019_2/xrt_201920.2.3.0_7.7.1908-xrt.rpm) [xrt_201920.2.3.0_7.7.1908-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.8.0/Patches/XRT_2019_2/xrt_201920.2.3.0_7.7.1908-aws.rpm) | N/A |
 

diff --git a/Vitis/examples/xilinx_2020.2 b/Vitis/examples/xilinx_2020.2
diff --git a/Vitis/tools/create_vitis_afi.sh b/Vitis/tools/create_vitis_afi.sh
@@ -279,4 +279,10 @@ echo ${timestamp}_agfi_id.txt
 
 #STEP 6
 #Create .awsxclbin
-/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
+
+if [ "$RELEASE_VER" == "2020.2" ]
+then                            
+	/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
+else
+	/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
+fi                                              
diff --git a/Vitis/vitis_xrt_version.txt b/Vitis/vitis_xrt_version.txt
@@ -1,4 +1,4 @@
 2019.2:9e13d57c4563e2c19bf5f518993f6e5a8dadc18a
 2020.1:12115fd4054cb46a5ade62fafa74c523f59116e6
 2020.1:d09c4a458c16e8d843b3165dcf929c38f7a32b6f
-
+2020.2:77d5484b5c4daa691a7f78235053fb036829b1e9
diff --git a/docs/on_premise_licensing_help.md b/docs/on_premise_licensing_help.md
@@ -3,14 +3,19 @@
 **NOTE: If you are developing on the AWS cloud and using AWS FPGA Developer AMI provided on AWS Marketplace, you can skip this document.**
 
 This document helps developers who choose to develop on-premises with specifying and licensing AWS-compatible Xilinx tools for use with the AWS FPGA HDK.
+## Requirements for AWS HDK 1.4.18+ (2020.2)
+ * Xilinx Vivado or Vitis v2020.2
+ * License: EF-VIVADO-SDX-VU9P-OP
+ * URL: https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.2_1118_1232.tar.gz
+ * MD5 SUM Value: 523e8596f114ab5e389c14df50ecb1d8
 
 ## Requirements for AWS HDK 1.4.16+ (2020.1)
  * Xilinx Vivado or Vitis v2020.1
  * License: EF-VIVADO-SDX-VU9P-OP
  * URL: https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.1_0602_1208.tar.gz
  * MD5 SUM Value: b018f7b331ab0446137756156ff944d9
 
- ## Requirements for AWS HDK 1.4.13+ (2019.2)
+## Requirements for AWS HDK 1.4.13+ (2019.2)
  * Xilinx Vivado or Vitis v2019.2
  * License: EF-VIVADO-SDX-VU9P-OP
  * URL: https://www.xilinx.com/member/forms/download/xef-vitis.html?filename=Xilinx_Vitis_2019.2_1106_2127.tar.gz

diff --git a/hdk/README.md b/hdk/README.md
@@ -66,6 +66,8 @@ For more details on the examples, see the [examples table](./cl/examples/cl_exam
 | 1.4.11-1.4.x | 2019.1 | v1.7.0 (Xilinx Vivado 2019.1) |
 | 1.4.11-1.4.x | 2019.2 | v1.8.x (Xilinx Vivado 2019.2) |
 | 1.4.16-1.4.x | 2020.1 | v1.9.x (Xilinx Vivado 2020.1) |
+| 1.4.18-1.4.x | 2020.2 | v1.10.x (Xilinx Vivado 2020.2) |
+
 
 * The FPGA Developer Kit version is listed in [hdk_version.txt](./hdk_version.txt)
 

diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl
@@ -19,7 +19,7 @@ package require tar
 set TOP top_sp
 
 ## Replace with the name of your module
-set CL_MODULE cl_dram_dma 
+set CL_MODULE cl_dram_dma
 
 #################################################
 ## Command-line Arguments
@@ -39,7 +39,7 @@ set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
 set VDEFINES            [lindex $argv 13]
 ##################################################
-## Flow control variables 
+## Flow control variables
 ##################################################
 set cl.synth   1
 set implement  1
@@ -147,6 +147,9 @@ set_msg_config -id {DRC CKLD-2}          -suppress
 set_msg_config -id {DRC REQP-1853}       -suppress
 set_msg_config -id {Timing 38-436}       -suppress
 
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 # Check that an email address has been set, else unset notify_via_sns
 
 if {[string compare $notify_via_sns "1"] == 0} {
@@ -159,7 +162,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 ##################################################
-### Strategy options 
+### Strategy options
 ##################################################
 switch $strategy {
     "BASIC" {
@@ -200,7 +203,7 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
 source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
@@ -254,7 +257,7 @@ if {$implement} {
       # Apply Clock Properties for Clock Table Recipes
       ##################################################
       puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
-      
+
       # Apply properties to clocks
       source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
 
@@ -385,5 +388,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
-
-
diff --git a/hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -37,6 +37,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################

diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl
@@ -39,7 +39,7 @@ set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
 set VDEFINES            [lindex $argv 13]
 ##################################################
-## Flow control variables 
+## Flow control variables
 ##################################################
 set cl.synth   1
 set implement  1
@@ -134,6 +134,9 @@ set_msg_config -id {Synth 8-3848}        -suppress
 set_msg_config -id {Synth 8-3917}        -suppress
 set_msg_config -id {Opt 31-430}          -suppress
 
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
 
 # Check that an email address has been set, else unset notify_via_sns
@@ -148,7 +151,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 ##################################################
-### Strategy options 
+### Strategy options
 ##################################################
 switch $strategy {
     "BASIC" {
@@ -187,14 +190,14 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
 source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
 
 source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
 #################################################################
-#### Do not remove this setting. Need to workaround bug 
+#### Do not remove this setting. Need to workaround bug
 ##################################################################
 set_param hd.clockRoutingWireReduction false
 ##################################################
@@ -236,7 +239,7 @@ if {$implement} {
       # Apply Clock Properties for Clock Table Recipes
       ##################################################
       puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
-      
+
       # Apply properties to clocks
       source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
 
@@ -365,5 +368,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
-
-
diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl
@@ -21,7 +21,7 @@ set VDEFINES $VDEFINES
 create_project -in_memory -part [DEVICE_TYPE] -force
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";

diff --git a/hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -37,6 +37,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################

diff --git a/hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -29,6 +29,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################