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Merge pull request #547 from aws/REL_v1_4_23
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@kyyalama2
kyyalama2 authored Feb 9, 2022
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3 changes: 3 additions & 0 deletions .gitmodules
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Expand Up @@ -14,3 +14,6 @@
[submodule "Vitis/examples/xilinx_2021.1"]
path = Vitis/examples/xilinx_2021.1
url = https://github.com/Xilinx/Vitis_Accel_Examples
[submodule "Vitis/examples/xilinx_2021.2"]
path = Vitis/examples/xilinx_2021.2
url = https://github.com/Xilinx/Vitis_Accel_Examples
19 changes: 16 additions & 3 deletions Jenkinsfile
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Expand Up @@ -126,15 +126,16 @@ task_label = [
]

// Put the latest version last
def xilinx_versions = [ '2021.1' ]
def vitis_versions = ['2021.1' ]
def xilinx_versions = [ '2021.2' ]
def vitis_versions = ['2021.2' ]

// We want the default to be the latest.
def default_xilinx_version = xilinx_versions.last()

def xsa_map = [
'2020.2' : [ 'DYNAMIC':'dyn'],
'2021.1' : [ 'DYNAMIC':'dyn']
'2021.1' : [ 'DYNAMIC':'dyn'],
'2021.2' : [ 'DYNAMIC':'dyn']
]

def vitis_example_default_map = [
Expand All @@ -161,6 +162,12 @@ def vitis_example_default_map = [
'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm'
],
'2021.2' : [
'Hello_World_1ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_helloworld',
'Gmem_2Banks_2ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_gmem_2banks',
'Kernel_Global_Bw_4ddr': 'Vitis/examples/xilinx/performance/kernel_global_bandwidth',
'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug'
],
]

def simulator_tool_default_map = [
Expand Down Expand Up @@ -193,6 +200,12 @@ def simulator_tool_default_map = [
'vcs': 'synopsys/vcs-mx/R-2020.12',
'questa': 'questa/2020.4',
'ies': 'incisive/15.20.083'
],
'2021.2' : [
'vivado': 'xilinx/Vivado/2021.2',
'vcs': 'synopsys/vcs-mx/R-2020.12',
'questa': 'questa/2020.4',
'xcelium': '20.09.006'
]
]

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16 changes: 11 additions & 5 deletions Jenkinsfile_int_sims
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Expand Up @@ -36,7 +36,7 @@ task_label = [
]

// Put the latest version last
def xilinx_versions = [ '2021.1' ]
def xilinx_versions = [ '2021.2' ]

// We want the default to be the latest.
def default_xilinx_version = xilinx_versions.last()
Expand Down Expand Up @@ -71,6 +71,12 @@ def simulator_tool_default_map = [
'vcs': 'synopsys/vcs/R-2020.12',
'questa': 'questa/2020.4',
'ies': 'incisive/15.20.083'
],
'2021.2' : [
'vivado': 'xilinx/Vivado/2021.2',
'vcs': 'synopsys/vcs/R-2020.12',
'questa': 'questa/2020.4',
'xcelium': 'xcelium/20.09.006'
]
]

Expand Down Expand Up @@ -156,7 +162,7 @@ if (test_sims) {
def simulators = ['vivado']
def sim_nodes = [:]
if(params.internal_simulations) {
simulators = ['vcs', 'ies', 'questa', 'vivado']
simulators = ['vcs', 'xcelium', 'questa', 'vivado']
}

for (x in cl_names) {
Expand All @@ -165,7 +171,7 @@ if (test_sims) {
String xilinx_version = y
String cl_name = x
String simulator = z
if((cl_name == 'cl_vhdl_hello_world') && (simulator == 'ies')) {
if((cl_name == 'cl_vhdl_hello_world') && (simulator == 'xcelium')) {
println ("Skipping Simulator: ${simulator} CL: ${cl_name}")
continue;
}
Expand All @@ -179,7 +185,7 @@ if (test_sims) {
def tool_module_map = simulator_tool_default_map.get(xilinx_version)
String vcs_module = tool_module_map.get('vcs')
String questa_module = tool_module_map.get('questa')
String ies_module = tool_module_map.get('ies')
String xcelium_module = tool_module_map.get('xcelium')
String vivado_module = tool_module_map.get('vivado')

if(params.internal_simulations) {
Expand All @@ -199,7 +205,7 @@ if (test_sims) {
module load ${vivado_module}
module load ${vcs_module}
module load ${questa_module}
module load ${ies_module}
module load ${xcelium_module}
source $WORKSPACE/hdk_setup.sh
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --simulator ${simulator} --batch 'TRUE'
"""
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36 changes: 18 additions & 18 deletions README.md
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Expand Up @@ -50,16 +50,17 @@ AWS marketplace offers multiple versions of the FPGA Developer AMI. The followin

## Xilinx tool support

| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version |
|-----------|-----------|------|
| 1.4.21+ | 2021.1 | v1.11.X (Xilinx Vivado/Vitis 2021.1) |
| 1.4.18+ | 2020.2 | v1.10.X (Xilinx Vivado/Vitis 2020.2) |
| 1.4.16+ | 2020.1 | v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1) |
| 1.4.13+ | 2019.2 | v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2) |
| 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) |
| 1.4.8 - 1.4.15b | 2018.3 | v1.6.0-v1.6.X (Xilinx Vivado/SDx 2018.3) |
| 1.4.3 - 1.4.15b | 2018.2 | v1.5.0-v1.5.X (Xilinx Vivado/SDx 2018.2) |
|⚠️ 1.3.7 - 1.4.15b | 2017.4 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) ⚠️|
| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version |
|-----------------------|------------------------|---------------------------------------------|
| 1.4.23+ | 2021.2 | v1.12.X (Xilinx Vivado/Vitis 2021.2) |
| 1.4.21+ | 2021.1 | v1.11.X (Xilinx Vivado/Vitis 2021.1) |
| 1.4.18+ | 2020.2 | v1.10.X (Xilinx Vivado/Vitis 2020.2) |
| 1.4.16+ | 2020.1 | v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1) |
| 1.4.13+ | 2019.2 | v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2) |
| 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) |
| 1.4.8 - 1.4.15b | 2018.3 | v1.6.0-v1.6.X (Xilinx Vivado/SDx 2018.3) |
| 1.4.3 - 1.4.15b | 2018.2 | v1.5.0-v1.5.X (Xilinx Vivado/SDx 2018.2) |
| ⚠️ 1.3.7 - 1.4.15b | 2017.4 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) ⚠️ |

⚠️ Developer kit release v1.4.16 will remove support for Xilinx 2017.4, 2018.2, 2018.3 toolsets. While developer kit release v1.4.16 onwards will not support older Xilinx tools, you can still use them using HDK releases v1.4.15b or earlier.
Please check out [the latest v1.4.15b release tag from Github](https://github.com/aws/aws-fpga/releases/tag/v1.4.15b) to use Xilinx 2017.4, 2018.2, 2018.3 toolsets.
Expand All @@ -71,10 +72,10 @@ For software-defined development please look at the runtime compatibility table

### End of life Announcements

| Xilinx Tool version | State | Statement |
|-----------|-----------|------|
| 2017.1 | 🚫 Deprecated on 09/01/2018 | Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) [reached end-of-life](https://forums.aws.amazon.com/ann.jspa?annID=6068). |
| 2017.4 | ⚠️ Upcoming deprecation on 12/31/2021 | Support for Xilinx 2017.4 toolsets will be deprecated on 12/31/2021. Please check our [forum announcement for more details](https://forums.aws.amazon.com/ann.jspa?annID=8949). |
| Xilinx Tool version | State | Statement |
|-----------|-----------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| 2017.1 | 🚫 Deprecated on 09/01/2018 | Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) [reached end-of-life](https://forums.aws.amazon.com/ann.jspa?annID=6068). |
| 2017.4 | 🚫 Deprecated on 12/31/2021 | [Support for Xilinx 2017.4 toolsets was deprecated on 12/31/2021](https://forums.aws.amazon.com/ann.jspa?annID=8949). |

## Hardware Development Kit (HDK)

Expand Down Expand Up @@ -123,7 +124,7 @@ The [SDK directory](./sdk/README.md) includes the runtime environment required t
* 1-8 Xilinx UltraScale+ VU9P based FPGA slots
* Per FPGA Slot, Interfaces available for Custom Logic(CL):
* One x16 PCIe Gen 3 Interface
* Four DDR4 RDIMM interfaces (with ECC)
* Four DDR4 RDIMM interfaces (72-bit with ECC, 16 GiB each; 64 GiB total)
* AXI4 protocol support on all interfaces
* User-defined clock frequency driving all CL to Shell interfaces
* Multiple free running auxiliary clocks
Expand Down Expand Up @@ -219,8 +220,7 @@ Documentation is located throughout this developer kit and the table below conso

# Developer Support

* The [**Amazon FPGA Development User Forum**](https://forums.aws.amazon.com/forum.jspa?forumID=243&start=0) is the first place to go to post questions, learn from other users and read announcements.
* We recommend joining the [AWS forums](https://forums.aws.amazon.com/forum.jspa?forumID=243) to engage with the FPGA developer community, AWS and Xilinx engineers to get help.
* [**AWS Re:Post**](https://repost.aws/) is the first place to go to post questions, learn from other users, to engage with the FPGA developer community, AWS and Xilinx engineers to get help.

* You could also file a [Github Issue](https://github.com/aws/aws-fpga/issues) for support. We prefer the forums as this helps the entire community learn from issues, feedback and answers.
* You could also file a [Github Issue](https://github.com/aws/aws-fpga/issues) for support. We prefer AWS Re:Post as this helps the entire community learn from issues, feedback and answers.
* Click the "Watch" button in GitHub upper right corner to get regular updates.
3 changes: 3 additions & 0 deletions RELEASE_NOTES.md
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Expand Up @@ -2,6 +2,9 @@

**NOTE:** See [ERRATA](./ERRATA.md) for unsupported features

## Release 1.4.22
* FPGA developer kit now supports Xilinx Vivado/Vitis 2021.2

## Release 1.4.22
* FPGA developer kit update to upgrade Virtual Ethernet to support jumbo frames using newer versions of dpdk/pktgen

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23 changes: 2 additions & 21 deletions SDAccel/FAQ.md
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Expand Up @@ -82,25 +82,6 @@ A: We support creating AFI's from CL's that have been built to work at Frequenci
# Additional Resources

* The [AWS SDAccel README](README.md).
* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html?resultsTablePreSelect=xlnxdocumenttypes:SeeAll#documentation)
* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/legacy-tools/sdaccel.html)
* [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples)

* Links pointing to **2017.4** version of the user guides
* [UG1023: SDAccel Environment User Guide][UG1023 2017.4]
* [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.4]
* [UG1207: SDAccel Environment Optimization Guide][UG1207 2017.4]
* [UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.4]
* [SDAccel_landing_page](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html)
* [Vivado HLS landing page](https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
* [Vivado landing page](https://www.xilinx.com/products/design-tools/vivado.html)
* [SDAccel Environment User Guide](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1023-sdaccel-user-guide.pdf)
* [SDAccel Intro Tutorial](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1021-sdaccel-intro-tutorial.pdf)
* [SDAccel Environment Optimization Guide](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1207-sdaccel-optimization-guide.pdf)
* [Vivado Design Methodology](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf)
* [2017.4 SDAccel User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf)
* [2017.4 SDAccel Intro Tutorial](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf)
* [2017.4 SDAccel Environment Optimization Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf)
* [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html#documentation)
* [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples)
* [AWS SDAccel Readme](README.md)
* [Debug HLS Performance: Limited memory ports](./docs/SDAccel_HLS_Debug.md)
* [Debug HLS Performance: Limited memory ports](./docs/SDAccel_HLS_Debug.md)
37 changes: 0 additions & 37 deletions SDAccel/docs/On_Premises_Development_Steps.md
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Expand Up @@ -138,40 +138,3 @@ The steps required to deploy and execute your uploaded applocation are the same
- Execute your application

All these are described in the [AWS SDAccel README]


# Additional Resources

Xilinx web portal for [Xilinx SDAccel documentation] and for [Xilinx SDAccel GitHub repository]

Links pointing to **2017.4** version of the user guides

[UG1023: SDAccel Environment User Guide][UG1023 2017.4]

[UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.4]

[UG1207: SDAccel Environment Optimization Guide][UG1207 2017.4]

[UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.4]

[SDAccel_landing_page]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html
[VHLS_landing_page]: https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
[Vivado_landing_page]: https://www.xilinx.com/products/design-tools/vivado.html

[latest SDAccel Environment User Guide]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1023-sdaccel-user-guide.pdf
[latest UG1021]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1021-sdaccel-intro-tutorial.pdf
[latest SDAccel Environment Optimization Guide]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1207-sdaccel-optimization-guide.pdf
[latest UG949]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf
[latest UG902]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug902-vivado-high-level-synthesis.pdf

[UG1023 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf
[UG1021 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf
[UG1207 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf
[UG1238 2017.4]:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1238-sdx-rnil.pdf
[Xilinx SDAccel documentation]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html#documentation
[Xilinx SDAccel GitHub repository]: https://github.com/Xilinx/SDAccel_Examples

[SDAccel download and License instructions]:https://github.com/aws/aws-fpga/blob/master/hdk/docs/on_premise_licensing_help.md
[Vivado download]:https://www.xilinx.com/products/design-tools/acceleration-zone/ef-vivado-sdx-vu9p-op-fl-nl.html
[SDAccel Download Page]: https://www.xilinx.com/registration/sign-in.html?oamProtectedResource=wh%3Dwww.xilinx.com%20wu%3D%2Fmember%2Fforms%2Fdownload%2Fxef.html%3Ffilename%3DXilinx_SDx_op_2017.1_sdx_0715_1_Lin64.bin%26akdm%3D0%20wo%3D1%20rh%3Dhttp%3A%2F%2Fwww.xilinx.com%20ru%3D%252Fmember%252Fforms%252Fdownload%252Fxef.html%20rq%3Dfilename%253DXilinx_SDx_op_2017.1_sdx_0715_1_Lin64.bin%2526akdm%253D0
[AWS SDAccel Readme]: ../README.md
13 changes: 3 additions & 10 deletions SDAccel/docs/SDAccel_Guide_AWS_F1.md
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Expand Up @@ -2,7 +2,7 @@
*It is assumed that the reader has run the instructions found in the [AWS SDAccel README] successfully*


This document provides a detailed reference to the [SDAccel Development Environment][SDAccel_landing_page] and its use with AWS F1 FPGA instances.
This document provides a detailed reference to the SDAccel Development Environment and its use with AWS F1 FPGA instances.

The SDAccel environment allows kernels expressed in OpenCL or C/C++ to be accelerated by implementing them in custom FPGA hardware. The flexible SDAccel Development Environment also allows the acceleration to be performed using pre-existing RTL designs.

Expand All @@ -18,7 +18,7 @@ In addition, you can review the following useful documents:

SDAccel uses a compiler named `xocc` which can be thought of as similar to the GNU gcc compiler -i.e. it allows you to compile source code to create Xilinx object (.xo) files and then can link said .xo files together to create an executable program; the .xo files contain an RTL representation of the accelerated kernels and the executable program is the design to be programmed onto the AWS F1 FPGA.

When the source code is OpenCL or C/C++ the [Vivado High-Level Synthesis (HLS)][VHLS_landing_page] tool is used under-the-hood to create the RTL that implements the custom hardware to meet the required performance and then an .xo file is created using the [Vivado toolchain][Vivado_landing_page].
When the source code is OpenCL or C/C++ the Vivado High-Level Synthesis (HLS) tool is used under-the-hood to create the RTL that implements the custom hardware to meet the required performance and then an .xo file is created using the [Vivado toolchain][Vivado_landing_page].

When the source code is RTL, the Vivado toolchain creates the .xo file directly without using Vivado HLS to generate any RTL description.

Expand Down Expand Up @@ -165,15 +165,8 @@ Conversely, code which is simply a few lines of basic operations, and has no tas
# Additional Resources

* The [AWS SDAccel README](../README.md).
* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html?resultsTablePreSelect=xlnxdocumenttypes:SeeAll#documentation)
* [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples)
* [Xilinx SDAccel landing page](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html)
* [Vivado landing page](https://www.xilinx.com/products/design-tools/vivado.html)
* [SDAccel Environment User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf)
* [SDAccel Intro Tutorial](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf)
* [SDAccel Environment Optimization Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf)
* [UltraFast Design Methodology Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug949-vivado-design-methodology.pdf)
* [Vivado High Level Synthesis User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug902-vivado-high-level-synthesis.pdf)
* [Xilinx SDAccel landing page](https://www.xilinx.com/products/design-tools/legacy-tools/sdaccel.html)
* [On Premise Development steps](On_Premises_Development_Steps.md)
* [SDAccel Power Analysis](SDAccel_Power_Analysis.md)
* [FAQ](../FAQ.md)
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4 changes: 2 additions & 2 deletions Vitis/README.md
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Expand Up @@ -58,8 +58,8 @@ The F1 HW Target compile time is ~50 minutes, therefore, software and hardware e

* Sourcing the *vitis_setup.sh* script:
* Downloads and sets the correct AWS Platform:
* [AWS Vitis Platform](./aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2) that contains the dynamic hardware that enables Vitis kernels to run on AWS F1 instances.
* Valid platforms for shell_v04261818: `AWS_PLATFORM_201920_2` (Default) AWS F1 Vitis platform.
* AWS Vitis Platform that contains the dynamic hardware that enables Vitis kernels to run on AWS F1 instances.
* Valid platforms for shell_v04261818: `AWS_PLATFORM_201920_3` (Default) AWS F1 Vitis platform.
* Sets up the Xilinx Vitis example submodules.
* Installs the required libraries and package dependencies.
* Run environment checks to verify supported tool/lib versions.
Expand Down
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