Bug Fix Release

We have identified a bug in the flop_ccf.sv module that can potentially impact timing closure of designs.
The module is instantiated in sh_ddr.sv and inadvertently introduces a timing path on the reset logic.
Although there is no functional impact, it may increase Vivado tool’s effort in timing closure of design.
There should be no functional impact from this bug if your design has already met timing.

Please check ERRATA for more info.