Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA

This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol

A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Repository to store all design and testbench files for Senior Design

This repo contains golden vector and randomization testbenches for SRAM module.

This repository contains source code for labs and projects involving FPGA and Verilog based designs

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA

cryptography ip-cores in vhdl / verilog

A repository where I intend to upload most Hardware design projects I make.

My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.

Implementation of a low-power enconding technique.

This repository contains several VHDL codes of signal processing

Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

Library of reusable VHDL components

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

A project to design a test-bench for thermal and pressure conditions in which a CubeSat satellite is subjected in space.