This repository contains source code for past labs and projects involving FPGA and Verilog based designs
simulator
encoder
decoder
priority
verilog
xilinx
testbenches
multiplexer
comparator
adder
system-verilog
xilinx-vivado
half-adder
traffic-light-controller
full-adder
ripple-adder
look-ahead-adder
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Updated
Oct 2, 2019 - Verilog