This repository contains source code for past labs and projects involving FPGA and Verilog based designs
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Updated
Oct 2, 2019 - Verilog
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Binary adder implementation in the Game of Life written in JavaScript using canvas.
A 4bit Multiplier in VHDL
Digital System Design Lab Codes using Verilog
A simulation where I can connect virtual logic gates and build virtual CIs.
A Java binary calculator based on a system of gates
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
Different adders code in VHDL and Comparison
This repository contains HWs and material from the nand to tetris course
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.
A repository for some modules I made while learning Verilog
Assignment 3, Digital Logic Design Lab, Spring 2021, IIT Bombay
A Java program that converts a binary number into it's two's complement equivalent. This is used within the SimpleBinaryCalculator repository.
Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦
CSE-2112 Digital Syatem Design LAb
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