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Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

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DFF.v
DFF.v
 
 
DFF_clr.v
DFF_clr.v
 
 
JKFF.v
JKFF.v
 
 
JKFF_using_DFF.v
JKFF_using_DFF.v
 
 
License
License
 
 
PIPO_bidirectional.v
PIPO_bidirectional.v
 
 
README.md
README.md
 
 
SIPO_behave.v
SIPO_behave.v
 
 
async_dualram_16X8.v
async_dualram_16X8.v
 
 
async_dualram_tb.v
async_dualram_tb.v
 
 
async_fifo.v
async_fifo.v
 
 
async_fifo_tb.v
async_fifo_tb.v
 
 
async_ram_16X8.v
async_ram_16X8.v
 
 
async_ram_tb.v
async_ram_tb.v
 
 
counter_4bit_asyn.v
counter_4bit_asyn.v
 
 
counter_4bit_upxdown.v
counter_4bit_upxdown.v
 
 
dff_tb.v
dff_tb.v
 
 
digi_clock_5hz.v
digi_clock_5hz.v
 
 
divideby2.v
divideby2.v
 
 
dualport_fileop.v
dualport_fileop.v
 
 
factorial_design.v
factorial_design.v
 
 
fifo.v
fifo.v
 
 
fifo_tb.v
fifo_tb.v
 
 
jkff_tb.v
jkff_tb.v
 
 
johnsoncounter_4bit.v
johnsoncounter_4bit.v
 
 
latch_SR.v
latch_SR.v
 
 
loadable_counter_5bit.v
loadable_counter_5bit.v
 
 
loadable_counter_5bit_tb.v
loadable_counter_5bit_tb.v
 
 
pipo_4bit.v
pipo_4bit.v
 
 
piso_4bit.v
piso_4bit.v
 
 
random_64bit.v
random_64bit.v
 
 
random_odd_range_test.v
random_odd_range_test.v
 
 
random_range_test.v
random_range_test.v
 
 
reg_4bit.v
reg_4bit.v
 
 
reg_4bit_clr.v
reg_4bit_clr.v
 
 
reg_4bit_str.v
reg_4bit_str.v
 
 
sipo_4bit.v
sipo_4bit.v
 
 
siso_4bit.v
siso_4bit.v
 
 
sr_flipflop.v
sr_flipflop.v
 
 
sync_dualram_16X8.v
sync_dualram_16X8.v
 
 
sync_dualram_tb.v
sync_dualram_tb.v
 
 
sync_ram_16X8.v
sync_ram_16X8.v
 
 
sync_ram_512X8.v
sync_ram_512X8.v
 
 
sync_ram_512X8_tb.v
sync_ram_512X8_tb.v
 
 
sync_ram_tb.v
sync_ram_tb.v
 
 
timer_sec.v
timer_sec.v
 
 
timeshared_clockedge_alt_approach.v
timeshared_clockedge_alt_approach.v
 
 
up_counter_4bit (.v
up_counter_4bit (.v
 
 
up_counter_4bit_tb.v
up_counter_4bit_tb.v
 
 
up_down_counter_4bit.v
up_down_counter_4bit.v
 
 
up_down_counter_4bit_tb.v
up_down_counter_4bit_tb.v
 
 

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Sequential-Logic-Circuits

Verilog Design and Testbench files for Flip Flop, Counters, Shift registers, Single and Dual port RAM, FIFO and other sequential logic circuits.

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Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

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testbenches verilog-hdl digital-design verilog-code

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