Skip to content

Issues: chipsalliance/fpga-tool-perf

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort

Issues list

Add support for RapidWright
#516 opened Nov 10, 2022 by tmichalak
Unify quicklogic with the VPR toolchain
#363 opened Oct 13, 2021 by acomodi
Why are there rows with all skipped?
#354 opened Sep 30, 2021 by mithro
Start from the FPGA type
#353 opened Sep 30, 2021 by mithro
Add Vexriscv/Litex designs for Oxide: No CFU / Trivial CFU / hps_accel CFU designs Related to designs being used to evaluate the performance in the FPGA Tool Perf
#350 opened Sep 23, 2021 by tcal-x
Use a disable list, not an enable list
#336 opened Aug 5, 2021 by mithro
ProTip! Mix and match filters to narrow down what you’re looking for.