Instructions for someone already familiar with CFU-Playground:

Use the proj/mnv2_first project. Cd to that directory.

Build the bitstream: make bitstream.

Go to the gateware build directory, soc/build/digilent_arty.mnv2_first/gateware/.

Look in the tcl script for the sources and copy them to the appropriate locations in fpga-tool-perf (it seems the pre-generated VexRiscv Verilog should go under third-party/)

Add project/cfuplayground.json with tests for "arty-a35t" and "arty-a100t" at 100MHz.

(Compare with the baselitex.json if necessary)