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yass 2018/02/25
cache line
ãƒªãƒ³ã‚¯
Why do CPUs have multiple cache levels?
This is a reader question from â€œjlforrestâ€ that seems worth answering in more detail than just a single sentence: I understand the need for a cache but I donâ€™t understand why there are multiple levels of cache instead of having just one larger level. In other words, letâ€™s say the L1 cache is 32K, the L2 cache is 256K, and the L3 cache is 2M, why not have a single 32K + 256K + 2M L1 cache? The shor
yass 2016/08/09
cache

cache line

CPU
ãƒªãƒ³ã‚¯
ã‚²ãƒ¼ãƒ ãƒ‘ãƒ•ã‚©ãƒ¼ãƒžãƒ³ã‚¹: ãƒ‡ãƒ¼ã‚¿æŒ‡å‘ãƒ—ãƒã‚°ãƒ©ãƒŸãƒ³ã‚°
.app 1 .dev 1 #11WeeksOfAndroid 13 #11WeeksOfAndroid Android TV 1 #Android11 3 #DevFest16 1 #DevFest17 1 #DevFest18 1 #DevFest19 1 #DevFest20 1 #DevFest21 1 #DevFest22 1 #DevFest23 1 #hack4jp 3 11 weeks of Android 2 A MESSAGE FROM OUR CEO 1 A/B Testing 1 A4A 4 Accelerator 6 Accessibility 1 accuracy 1 Actions on Google 16 Activation Atlas 1 address validation API 1 Addy Osmani 1 ADK 2 AdMob 32 Ads
yass 2015/08/21
cpu

cache

cache line
ãƒªãƒ³ã‚¯
Intel Haswell
Intel i7-4770 (Haswell), 3.4 GHz (Turbo Boost off), 22 nm. RAM: 32 GB (PC3-12800 cl11 cr2). L1 Data cache = 32 KB, 64 B/line, 8-WAY. L1 Instruction cache = 32 KB, 64 B/line, 8-WAY. L2 cache = 256 KB, 64 B/line, 8-WAY L3 cache = 8 MB, 64 B/line L1 Data Cache Latency = 4 cycles for simple access via pointer L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n
yass 2015/03/23
" 64-bytes range cross penalty = 5 cycles / 4096-bytes range cross penalty = 28 cycles "

haswell

intel

cpu

latency

bandwidth

cache line

cache

memory
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5. All programmer should know â€¢ L1 ã‚ãƒ£ãƒƒã‚·ãƒ¥å‚ç…§......................... 0.5 ns â€¢ åˆ†å²äºˆæ¸¬ãƒŸã‚¹............................ 5 ns â€¢ L2 ã‚ãƒ£ãƒƒã‚·ãƒ¥å‚ç…§........................... 7 ns â€¢ Mutex lock/unlock ........................... 25 ns â€¢ Main memory å‚ç…§...................... 100 ns 7. ã‚ãƒ£ãƒƒã‚·ãƒ¥ã‚³ãƒ’ãƒ¼ãƒ¬ãƒ³ãƒˆï¼Ÿ â€¢ è¤‡æ•°ã®CPUã‚³ã‚¢ã‹ã‚‰è¦‹ãˆã‚‹ãƒ¡ãƒ¢ãƒªã¯åŒä¸€ã§ãª ã„ã¨å›°ã‚‹ â€¢ ã¤ã¾ã‚Šè¤‡æ•°ã®CPUã‚³ã‚¢ã®ã‚ãƒ£ãƒƒã‚·ãƒ¥ã¯å¸¸ã«æœ€ æ–°ã®æƒ…å ±ã‚’ä¿æŒã—ã¦ãªã„ã¨å›°ã‚‹ â€¢ ã ãŒå¸¸ã«æœ€æ–°ã®æƒ…å ±ã‚’å…¨éƒ¨ã®ã‚ãƒ£ãƒƒã‚·ãƒ¥ã«å…¨ ã¦æ›¸ãç¶šã‘ã‚‹ã®ã¯é€Ÿåº¦ãŒå‡ºãªã„ã®ã§ã€ã¾ã‚‹ã§ æœ¬å½“ã«å…¨éƒ¨ã®ã‚ãƒ£ãƒƒã‚·
yass 2014/10/25
" Main memory å‚ç…§...................... 100 ns â€¢ QPIçµŒç”±ã§éš£ã®ãƒ¡ãƒ¢ãƒªå‚ç…§.............. 200 nsï½ž / éš£ã®CPUã®ã‚ãƒ£ãƒƒã‚·ãƒ¥ã¯ è‡ªåˆ†ã®ãƒ¡ã‚¤ãƒ³ãƒ¡ãƒ¢ãƒªã‚ˆã‚Šã‚‚é ã„ï¼ï¼ï¼Â "

CPU

cache

cache line

qpi

lock-free

counter
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CPU Caches
yass 2014/02/16
cpu

cache

memory

cache line
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Enhanced Intel SpeedStepÂ® Technology and Demand-Based Switching on Linux* - IntelÂ® Software Network
Using Intel.com Search You can easily search the entire Intel.com site in several ways. Brand Name: Core i9 Document Number: 123456 Code Name: Emerald Rapids Special Operators: â€œIce Lakeâ€, Ice AND Lake, Ice OR Lake, Ice* Quick Links You can also try the quick links below to see results for most popular searches. Product Information Support Drivers & Software
yass 2014/02/15
intel

prefetch

memory

bios

cache line
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yass 2013/06/15
" ä¾‹ãˆã° 4GHz ã® CPU ã§ 1 clock ã®é–“ã«å…‰ãŒé€²ã‚€è·é›¢ã‚’è€ƒãˆã‚‹ã¨ã€ 3Ã—1010Â [cm/s] / 4Ã—109[Hz] = 7.5 cm ã«ãªã‚Šã¾ã™ã€‚ "

CPU

memory

cache

cache line
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Robin Hood Hashing should be your default Hash Table implementation
A Random Walk Through Geek-Space Brain dumps and other ramblings from Sebastian Sylvan Robin Hood Hashing should be your default Hash Table implementation 8/May 2013 Thereâ€™s a neat variation on open-addressing based hash tables called Robin Hood hashing. This technique isnâ€™t very well-known, but it makes a huge practical difference because it both improves performance and space utilization compare
yass 2013/06/10
hash

open addressing hash

hashtable

robin hood hashing

cache line
ãƒªãƒ³ã‚¯
Direct Memory Alignment in Java
Summary: First in a quick(hopefully) series of posts on memory alignment in Java. This post introduces memory alignment, shows how to get memory aligned blocks, and offers an experiment and some results concerning unaligned memory performance. Since the first days of Java, one of the things you normally didn't need to worry about was memory. This was a good thing for all involved who cared little
yass 2013/05/26
java

cache line

cache

memory

ByteBuffer

offheap
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cache_coloring
cache coloringã¨ã¯ ãƒ—ãƒã‚°ãƒ©ãƒ ã®å®Ÿè¡Œé€Ÿåº¦ã‚’ä¸Šã’ã‚‹ãŸã‚ã«ã¯ã€CPUãŒæŒã£ã¦ã„ã‚‹cacheã‚’ã„ã‹ã«ä¸Šæ‰‹ã«ä½¿ã†ã‹ãŒé‡è¦ã«ãªã£ã¦ãã¾ã™ã€‚ ãƒ—ãƒã‚°ãƒ©ãƒ ã§å·¥å¤«ã™ã‚‹äº‹ã«ã‚ˆã£ã¦ã€cacheã®missçŽ‡ã‚’ä¸‹ã’ã¦ã€å®Ÿè¡Œé€Ÿåº¦ã‚’ä¸Šã’ã‚‹äº‹ãŒã§ãã¾ã™ã€‚ cacheã®coloringã¨ã¯ã€cacheã®missçŽ‡ã‚’ä¸‹ã’ã‚‹ãŸã‚ã®ãƒ—ãƒã‚°ãƒ©ãƒ ãƒ†ã‚¯ãƒ‹ãƒƒã‚¯ã§ã™ã€‚ cacheã®ä»•çµ„ã¿ å‰ç¨‹ è©±ã‚’ç°¡å˜ã«ã™ã‚‹ãŸã‚ã«ã€ cacheã®æ–¹å¼ã¯ã€direct mappedã€‚ cacheã®1ãƒ©ã‚¤ãƒ³ã®ã‚µã‚¤ã‚ºã¯16bytesã€‚ cacheã‚µã‚¤ã‚ºã¯1KBã€‚ ã¨ã—ã¾ã™ã€‚ cacheã®æ§‹æˆ <--16bytes--> +-----------+ index0 | | +-----------+ index1 | | +-----------+ index2 | | +-----------+ index3 | | +-----------+
yass 2013/04/27
" ç¾åœ¨ã®Linuxã‚«ãƒ¼ãƒãƒ«ã§ã¯ã€task structã‚’ç½®ãã‚¢ãƒ‰ãƒ¬ã‚¹ã‚’ã€8ã®å€æ•°+Î±ã«ã—ã¦ã„ã¾ã™ã€‚Î±ã‚’ãƒ—ãƒã‚»ã‚¹ã«ã‚ˆã£ã¦ã„ã‚ã„ã‚å¤‰ãˆã¦ã‚„ã‚‹äº‹ã§ã€task structãŒåŒã˜cache lineã«å…¥ã‚‹äº‹ã‚’é˜²ã„ã§ã„ã¾ã™ã€‚"

cpu

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cache
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yass 2013/04/26
cpu

cache line

cache

programming

loop

memory
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yass 2013/04/26
cpu

cache line

cache

programming

loop

compiler
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yass 2013/04/26
cpu

cache line

memory

programming

loop

cache
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Aligned vs. unaligned memory access - Alex on Linux
yass 2012/12/24
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Why interrupt affinity with multiple cores is not such a good thing - Alex on Linux
Why interrupt affinity with multiple cores is not such a good thing One of the features of x86 architecture is ability to spread interrupts evenly among multiple cores. Benefits of such configuration seems to be obvious. Interrupts consume CPU time and by spreading them on all cores we avoid bottle-necks. Iâ€™ve written an article explaining this mechanism in greater detail. Yet let me remind you ho
yass 2012/12/23
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