[B! vhdl] masterqã®ãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯

masterq id:masterq

vhdlã«é–¢ã™ã‚‹masterqã®ãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯ (38)

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GitHub - antonblanchard/microwatt: A tiny Open POWER ISA softcore written in VHDL 2008
masterq 2023/07/22
vhdl

cpu

powerpc

power

ghdl

fpga

linux
ãƒªãƒ³ã‚¯
CXXRTL, a Yosys Simulation Backend
masterq 2021/11/20
Icarus Verilogã‚„Verilatorã¨ã¯åˆ¥ã«YosysãŒå…¬å¼ã«ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ã¨ã—ã¦C++ã‚³ãƒ¼ãƒ‰ã‚’åãã‚ˆã†ã«ãªã£ãŸã®ã‹

yosys

simulator

verilog

vhdl
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GitHub - okuoku/nanocpu: 8bit CPU for CPLD, for my blog article
masterq 2021/10/22
ã‚ã¨ã§èªã‚€

cpu

cpld

vhdl

8bit
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GitHub - cpldcpu/MCPU: MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD
masterq 2021/10/22
ã‚ã¨ã§èªã‚€

cpu

cpld

vhdl

8bit
ãƒªãƒ³ã‚¯
Design and Implementation of FPGA based Wi-Fi MAC Transmitter
masterq 2021/01/16
ã‚ˆãèªã‚“ã§ãªã„ã‚“ã ã‘ã©PHYã¯ã©ã†ã—ãŸã‚“ã ã‚ã†ã‹

wifi

wireless

network

fpga

hardware

vhdl

hdl

paper

mac

xilinx
ãƒªãƒ³ã‚¯
w11/rtl/sys_gen/w11a/arty/README.md at master Â· wfjm/w11
masterq 2020/07/16
"2019-06-05: reduce clock to 72 MHz, Vivado 2919.1 fails with 75 MHz" ã‚¨ã‚¨ã€‚ã€‚ã€‚æ€–ããªã„ã§ã™ã‹ã€‚ã€‚ã€‚

fpga

vivado

vhdl

hdl

hz
ãƒªãƒ³ã‚¯
GitHub - RobertPeip/FPGBA: GBA on FPGA
masterq 2019/12/28
Terasic DE2-115/Terasic DE-10

fpga

vhdl

gameboy
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GitHub - AntonMause/rv16poc: 16 bit RISC-V proof of concept
masterq 2019/09/05
ãªã‚“ã¨

cpu

risc-v

16bit

vhdl
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GitHub - MiSTer-devel/X68000_MiSTer: Sharp X68000 for MiSTer
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masterq 2019/05/04
"FDD images on secondary SD card/HDD images (SASI only!) on secondary SD card"

x68000

fpga

hdl

verilog

vhdl
ãƒªãƒ³ã‚¯
http://vmchale.com/static/resume.pdf
masterq 2018/10/05
resume

sample

haskell

vhdl

language

1page
ãƒªãƒ³ã‚¯
GitHub - Domipheus/RPU: Basic RISC-V CPU implementation in VHDL.
masterq 2018/09/27
vhdl

cpu

fpga

risc-v
ãƒªãƒ³ã‚¯
SNES on FPGA âˆµã‚¹ãƒ¼ãƒ•ã‚¡ãƒŸé–‹ç™ºã®ãƒ¡ãƒ¢ãƒ©ãƒ³ãƒ€ãƒ âˆ´
SNES on FPGAã‚¹ãƒ¼ãƒ•ã‚¡ãƒŸé–‹ç™ºã®ãƒ¡ãƒ¢ãƒ©ãƒ³ãƒ€ãƒ DE2-115 FPGA board (1 chip SNES) ã‚¹ãƒ¼ãƒ•ã‚¡ãƒŸã¯éŠã¶ãŸã‚ã®ã‚‚ã®ã§ã€é–‹ç™ºã™ã‚‹ãŸã‚ã®ã‚‚ã®ã§ã¯ã‚ã‚Šã¾ã›ã‚“ã€‚ SFCã€ã¤ã¾ã‚Šã‚¹ãƒ¼ãƒ•ã‚¡ãƒŸã‚’FPGAã§è‡ªä½œã—ãŸã€ã¨ã„ã†ãŠè©±ã€‚ ãƒ•ã‚¡ãƒŸã‚³ãƒ³ã®æ™‚ä»£ã€å½“æ™‚ã¨ã—ã¦ã¯é«˜ã„æ€§èƒ½ã ã£ãŸãŒãã‚Œä»¥ä¸Šã«å®Ÿç¾ã§ããªã‹ã£ãŸã‚¯ãƒªã‚¨ã‚¤ã‚¿ãƒ¼ãŸã¡ã®ä¸–ç•ŒãŒã€ ã‚¹ãƒ¼ãƒ•ã‚¡ãƒŸã®æ™‚ä»£ã«ãªã‚Šå°‘ã—ãšã¤å®Ÿç¾ã—ã¤ã¤ã‚ã£ãŸï¼ˆãã‚Œã¯ã‚‚ã†ICãŒç«ã‚’å™´ã‹ã‚“ãŒã”ã¨ãï¼‰ã€‚ ãƒ‡ã‚¶ã‚¤ãƒŠãƒ¼ã€ãƒãƒˆãƒ«ãƒ—ãƒã‚°ãƒ©ãƒžã€ãƒ‰ãƒƒã‚¿ãƒ¼ã€ã‚µã‚¦ãƒ³ãƒ‰ãƒ—ãƒã‚°ãƒ©ãƒžâ€¦ å½¼ã‚‰ã®æ´å²ã®ä¸ã§ç´¡ãŒã‚Œã¦ããŸã‚‚ã®ã¯ãªã‚“ã ã£ãŸã®ã‹ã€‚ ã‚¹ãƒ¼ãƒ•ã‚¡ãƒŸäº’æ›æ©Ÿã®è£½ä½œã€‚ãã‚Œã¯ã‚¹ãƒ¼ãƒ•ã‚¡ãƒŸã«ãŠã„ã¦æœ€å¾Œã®ã‚²ãƒ¼ãƒ ã¨ãªã‚‹ã€‚ â–¼ é–‹ç™ºç’°å¢ƒ ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢è¨˜è¿°è¨€èªž SFL+ã€VerilogHDLã€VHDL ä½¿ç”¨FPGAãƒœãƒ¼ãƒ‰ Terasic DE1 2005ï½ž Altera CycloneII ç´„18,000
masterq 2018/06/03
nintendo

snes

fpga

altera

hdl

vhdl

verilog
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GitHub - janestreet/hardcaml: Hardcaml is an OCaml library for designing hardware.
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masterq 2018/05/25
ocaml

hdl

verilog

vhdl
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HDL Coder
HDL Coder ã¯ã€MATLABÂ é–¢æ•°ã€SimulinkÂ ãƒ¢ãƒ‡ãƒ«ã€ãŠã‚ˆã³ StateflowÂ ãƒãƒ£ãƒ¼ãƒˆã‹ã‚‰ç§»æ¤ã‚„è«–ç†åˆæˆãŒå¯èƒ½ãª VerilogÂ® ãŠã‚ˆã³ VHDLÂ® ã‚³ãƒ¼ãƒ‰ã‚’ç”Ÿæˆã—ã€FPGAã€SoCã€ãŠã‚ˆã³ ASIC å‘ã‘ã®é«˜ä½è¨è¨ˆã‚’å¯èƒ½ã«ã—ã¾ã™ã€‚ç”Ÿæˆã•ã‚ŒãŸ HDL ã‚³ãƒ¼ãƒ‰ã¯ã€FPGA ãƒ—ãƒã‚°ãƒ©ãƒŸãƒ³ã‚°ã€ASIC ãƒ—ãƒãƒˆã‚¿ã‚¤ãƒ”ãƒ³ã‚°ã€ãŠã‚ˆã³é‡ç”£è¨è¨ˆã«ä½¿ç”¨ã§ãã¾ã™ã€‚ HDL Coder ã¯ã€AMDÂ®ã€IntelÂ®ã€Microchip ãƒœãƒ¼ãƒ‰ã§ã®ç”Ÿæˆã•ã‚ŒãŸã‚³ãƒ¼ãƒ‰ã®ãƒ—ãƒãƒˆã‚¿ã‚¤ãƒ”ãƒ³ã‚°ã‚’è‡ªå‹•åŒ–ã—ã€ASIC ãŠã‚ˆã³ FPGA ãƒ¯ãƒ¼ã‚¯ãƒ•ãƒãƒ¼ç”¨ã® IP ã‚³ã‚¢ã‚’ç”Ÿæˆã™ã‚‹ãƒ¯ãƒ¼ã‚¯ãƒ•ãƒãƒ¼ ã‚¢ãƒ‰ãƒã‚¤ã‚¶ãƒ¼ã‚’å‚™ãˆã¦ã„ã¾ã™ã€‚åˆæˆå‰ã«ã€é€Ÿåº¦ãŠã‚ˆã³é¢ç©ã®æœ€é©åŒ–ã€ã‚¯ãƒªãƒ†ã‚£ã‚«ãƒ«ãƒ‘ã‚¹ã®å¼·èª¿è¡¨ç¤ºã€ãƒªã‚½ãƒ¼ã‚¹ä½¿ç”¨é‡ã®æŽ¨å®šã®ç”Ÿæˆã‚’è¡Œã†ã“ã¨ãŒã§ãã¾ã™ã€‚HDL Coder ã¯ã€Simulink ãƒ¢ãƒ‡ãƒ«ã¨ç”Ÿæˆã•ã‚ŒãŸ Verilog ã‚„ VHD
masterq 2018/03/28
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matlab

simulink

hdl

generate

verilog

vhdl
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2.11BSD
masterq 2018/03/21
bsd

fpga

vhdl

os

kernel
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w11: PDP-11/70 CPU and SoC
masterq 2018/03/14
æ®‹å¿µãªãŒã‚‰VHDLã‹ãƒ¼ã€‚ã§ã‚‚ã“ã‚Œã‚’Verilogã«å†™çµŒã™ã‚Œã°å‹‰å¼·ã«ãªã‚‹ã®ã§ã¯ã€‚ "runs currently on Digilent Cmod A7 , Arty , Basys3 , Nexys4 DDR , Nexys4 , Nexys3 , Nexys2 and S3board boards"

dec

cpu

pdp11

fpga

vhdl

digilent
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FreeHDL index Page
A project to develop a free, open source, GPL'ed VHDL simulator for Linux! Project goals: To develop a VHDL simulator that: Has a graphical waveform viewer. Has a source level debugger. Is VHDL-93 compliant. Is of commercial quality. (on par with, say, V-System - it'll take us a while to get there, but that should be our aim) Is freely distributable - both source and binaries - like Linux itself.
masterq 2018/02/06
vhdl

simulater

debug

linux

c++

compiler
ãƒªãƒ³ã‚¯
Home
A modern, functional, hardware description language Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circ uits. The Clash compiler transf orms these high-level descriptions to low-level synthesizable VHDL, V
masterq 2017/12/30
ä»•äº‹ã§ä½¿ã„ãŸã„ã§ã™ã€‚ã€‚ã€‚

haskell

hdl

vhdl

fpga

verilog
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GitHub - SpinalHDL/SpinalHDL: Scala based HDL
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masterq 2017/07/22
Verilog/VHDLã‚’åãé«˜ä½åˆæˆè¨€èªžãªã®ã§ã—ã‚‡ã†ã‹ã€‚Chiselã«ã‚ˆã‚‹é«˜ä½åˆæˆã«ã¯å•é¡ŒãŒã‚ã‚‹ã¨ã®æŒ‡æ‘˜æœ‰ã‚Š

verilog

vhdl

hdl

scala
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GitHub - f32c/f32c: A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
masterq 2017/07/19
MIPSã¨RISC-Vã‚’å‘½ä»¤ã‚»ãƒƒãƒˆã«é¸ã¹ã‚‹ã‚‰ã—ã„

mips

risc-v

fpga

vhdl

hdl

cpu

lattice

altera

xilinx

arduino
ãƒªãƒ³ã‚¯
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