Hazard3 is a 3-stage RISC-V processor, implementing the RV32I instruction set and the following optional extensions: M: integer multiply/divide/modulo A : atomic memory operations, with AHB5 global exclusives C: compressed instructions Zicsr: CSR access Zba: address generation Zbb: basic bit manipulation Zbc: carry-less multiplication Zbs: single-bit manipulation Zbkb: basic bit manipulation for s
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