icarus-verilog

Star

Here are 70 public repositories matching this topic...

olofk / edalize

Star

An abstraction library for interfacing EDA tools

Updated Nov 22, 2024
Python

mshr-h / vscode-verilog-hdl-support

Sponsor

Star

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Nov 22, 2024
TypeScript

dpretet / async_fifo

Sponsor

Star

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

scarv / xcrypto

Star

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

unixb0y / SystemVerilogSHA256

Star

SHA256 in (System-) Verilog / Open Source FPGA Miner

fpga bitcoin mining verilog sha256 systemverilog icarus-verilog

Updated Mar 10, 2018
SystemVerilog

dpretet / svut

Sponsor

Star

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Updated Oct 22, 2024
Python

stnolting / neorv32-verilog

Star

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Nov 18, 2024
Verilog

sgherbst / svreal

Star

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

albertxie / iverilog-tutorial

Star

Quickstart guide on Icarus Verilog.

verilog signal icarus-verilog gtkwave csc258

Updated Jun 18, 2020
Verilog

yasnakateb / PipelinedARM

Star

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

aditeyabaral / DDCO-Lab-UE18CS207

Star

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

sifferman / fusesoc_template

Star

Example of how to get started with olofk/fusesoc.

vivado icestorm icarus-verilog yosys fusesoc tinyfpga-bx nexys-a7 nextpnr-ice40

Updated Jul 25, 2021
Python

Elphel / vdt-plugin

Star

mirror of https://git.elphel.com/Elphel/vdt-plugin

eclipse ide eclipse-plugin verilog vivado icarus-verilog gtkwave quartus cocotb

Updated Nov 29, 2017
Java

esynr3z / pyhdlsim

Star

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

addisonElliott / SCIC

Star

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

asic cpu digital simulation tcl rtl verilog synthesis icarus-verilog gate cadence

Updated Nov 29, 2018
Verilog

TheOneKevin / icarusext

Star

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

verilog vscode-extension icarus-verilog gtkwave verilog-testbenches

Updated Mar 4, 2023
TypeScript

yasnakateb / NoCRouter

Star

👶🏻 My first baby steps into the world of NoC

router verilog icarus-verilog verilog-hdl iverilog

Updated Sep 1, 2022
Verilog

SymbiFlow / XilinxUnisimLibrary

Star

Apache 2.0 licensed copy of the Xilinx Unisim library.

simulation xilinx vivado icarus-verilog icarus verilator

Updated Jul 22, 2020
Verilog

FPGAwars / toolchain-iverilog

Star

🌱 Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS

toolchain platformio icarus-verilog apio

Updated May 9, 2022
Verilog

GLADICOS / UART

Star

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

uart icarus-verilog systemc gtkwave systemc-model uart-verilog dut

Updated Sep 27, 2022
Verilog

Improve this page

Add a description, image, and links to the icarus-verilog topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the icarus-verilog topic, visit your repo's landing page and select "manage topics."

Learn more

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

icarus-verilog

Here are 70 public repositories matching this topic...

olofk / edalize

mshr-h / vscode-verilog-hdl-support

dpretet / async_fifo

scarv / xcrypto

unixb0y / SystemVerilogSHA256

dpretet / svut

stnolting / neorv32-verilog

sgherbst / svreal

albertxie / iverilog-tutorial

yasnakateb / PipelinedARM

aditeyabaral / DDCO-Lab-UE18CS207

sifferman / fusesoc_template

Elphel / vdt-plugin

esynr3z / pyhdlsim

addisonElliott / SCIC

TheOneKevin / icarusext

yasnakateb / NoCRouter

SymbiFlow / XilinxUnisimLibrary

FPGAwars / toolchain-iverilog

GLADICOS / UART

Improve this page

Add this topic to your repo