In late May of 2022, AWS released Graviton 3 to the general public. Graviton 3 was the first ARM CPU to introduce the SVE instruction set to a widely accessible server CPU. Before Graviton 3’s general availability, Neoverse N1 dominated the ARM server landscape. AWS’s previous flagship offering, Graviton 2, implements 64 Neoverse N1 cores at 2.5 GHz. Microsoft’s Azure and Oracle’s OCI both use Amp

How fast can it go? Sometimes you just want to know how fast your code can go, without benchmarking it. Sometimes you have benchmarked it and want to know how close you are to the maximum speed. Often you just need to know what the current limiting factor is, to guide your optimization decisions. Well this post is about that determining that speed limit1. It’s not a comprehensive performance evalu

At Hot Chips last week, IBM announced its new mainframe Z processor. It’s a big interesting piece of kit that I want to do a wider piece on at some point, but there was one feature of that core design that I want to pluck out and focus on specifically. IBM Z is known for having big L3 caches, backed with a separate global L4 cache chip that operates as a cache between multiple sockets of processor

Branch predictor: How many "if"s are too many? Including x86 and M1 benchmarks!2021-05-06 Some time ago I was looking at a hot section in our code and I saw this: if (debug) { log("..."); } This got me thinking. This code is in a performance critical loop and it looks like a waste - we never run with the "debug" flag enabled[1]. Is it ok to have if clauses that will basically never be run? Surely,

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TL;DR 分散システムにおいてキューを導入する場合、本当にキューが必要なのか再考すべき。そこが地獄の入り口だから。 システムの抽象 コンピュータの世界は、本来は0と1の信号の羅列が飛び交う無機質なものである。でも人類は信号だけですべてを語らず、様々な喩えを定義してきた。それはデスクトップ・ウィンドウ・マウスカーソルといったグラフィカルな表現に留まらず、パケットやカプセル化といった用語にロック・キュー・リスト・木などのアルゴリズムやデータ構造の世界にも自然に溶け込んでいる。これらはすべて人間の理解を助けるための喩え話に過ぎず、この喩えこそが人間のより直感的な理解をもたらす一方で、発想の制約を生み出してきた。 人間が大きなシステムを作るときも何らかの喩えを用いてシステム全体を整理する。アーキテクチャの「ポンチ絵」を描いて情報共有をするのは企業に勤めていれば経験した人も多いだろう。パワーポイン

Computer Architecture Today Informing the broad computing community about current activities, advances and future directions in computer architecture. SIMD Instructions Considered Harmful by David Patterson and Andrew Waterman on Sep 18, 2017 | Tags: Architecture, CPU, ISA, Parallelism In the process of writing a short introduction to RISC-V, we compared RISC-V vector code to SIMD. We were struck

コンピュータアーキテクチャの話 第481回 独自メニーコアチップでTop500 1位を獲得した中国の「神威・太湖之光」スパコン

テレビ会議を使用した配信講義開催のお知らせです。この「計算科学技術特論A」では「京」をはじめとするスーパーコンピュータなどを十分に活用するために培った技術を、広く公開して、次のフラッグシップ・スーパーコンピュータの完成時に速やかにそれを使いこなせる人材を育成し、シミュレーションを日本の基盤技術として発展させる土台を作ることを目指しております。最寄りの拠点にてご参加いただくことが可能で、資料なども公開予定です。お気軽にご参加ください。

Today, we gave a keynote presentation at the Open Networking Summit, where we shared details about Espresso, Google’s peering edge architecture—the latest offering in our Software Defined Networking (SDN) strategy. Espresso has been in production for over two years and routes 20 percent of our total traffic to the internet—and growing. It’s changing the way traffic is directed at the peering edge,

2016年10月24日に開催されたQCon Tokyo 2016での講演「A-3 今どきのアーキテクチャ設計戦略」の資料です。Read less