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DC-ROMA RISC-V AI PC, RISC-V MAINBOARD II FOR FRAMEWORK LAPTOP 13 The world's first up to 50 TOPS RISC-V Al PC Shop now DC-ROMA RISC-V MAINBOARD The first RISC-V mainboard compatible with Framework Laptop 13 Shop now WORLD'S FIRST RISC‑V LAPTOP GETS A MASSIVE UPGRADE AND EQUIPS WITH UBUNTU Octa-core RISC-V CPU Ubuntu pre-installed SpacemiT K1 SoC Shop now
Announcing the RISE RISC-V Runners: free, native RISC-V CI on GitHub – Rise: RISC-V Software Ecosystem
by Ludovic Henry, RISE Today, we are excited to announce the Early Availability of the RISE RISC-V Runners, a free, managed GitHub Actions runner service that gives any open source project access to real RISC-V hardware in their CI pipelines. No emulation, no cross-compilation hacks, no waitlist. Install a GitHub App, change one line in your workflow, and your jobs run on physical RISC-V boards. W
RISC-V Debugã®æœ€å°æ§‹æˆã‚’æ•´ç†ã™ã‚‹(1. 最å°æ§‹æˆã®æ•´ç†) - FPGA開発日記
RISC-V Debug Specã‚’èªã¿ãªãŒã‚‰ã€è‡ªä½œCPUã«ãƒ‡ãƒãƒƒã‚°æ©Ÿèƒ½ã‚’入れるãŸã‚ã®æ§‹æˆã‚’æ•´ç†ã—ã¦ã„る。 Debug Spec ã¯å¯¾è±¡ç¯„囲ãŒåºƒãã€æœ€åˆã«èªã‚€ã¨ã€ŒCPU ã«ä½•ã‚’è¿½åŠ ã™ã‚Œã°ã‚ˆã„ã®ã‹ã€ã¨ã€ŒCPU ã®å¤–ã«ä½•ã‚’ç½®ãã¹ãã‹ã€ãŒå°‘ã—見ãˆã¥ã‚‰ã„。 特ã«æ•´ç†ã—ãŸã„ã®ã¯ä»¥ä¸‹ã®ç‚¹ã 。 CPU ã®ä¸ã«ä½•ã‚’æŒã¤ã¹ãã‹ Debug Module(DM) ã¯ã©ã“ã¾ã§å¿…è¦ã‹ DTM / DMI / DM / HART ã®å¢ƒç•Œã¯ã©ã“㋠「最å°æ§‹æˆã€ã¨ã€Œä»•æ§˜æº–æ‹ ã€ã¯ã©ã“ã¾ã§ä¸€è‡´ã™ã‚‹ã‹ ã“ã“ã§ã¯ã¾ãšã€å˜ä¸€ hart を対象ã«ã—ãŸæœ€å°æ§‹æˆã«çµžã£ã¦æ•´ç†ã™ã‚‹ã€‚ å‚考文献：https://github.com/riscv/riscv-debug-spec/releases/download/1.0/riscv-debug-specification.pdf ã¾ãšå…¨ä½“æ§‹æˆ RISC-V Debugã®å…¨ä½“構æˆã¯ã€ã–ã£ãã‚Š
1人ã§1万個é‡ç”£ã€290円ã®ãƒžã‚¤ã‚³ãƒ³ãƒœãƒ¼ãƒ‰ã€ŒUIAPduinoã€ãƒ¼ãƒ¼ç›®æŒ‡ã™å…ˆã¯100å‡ã®æ£š - FabScene（ファブシーン）
「UIAPduinoã€ã¯290円（税込）ã®Arduino互æ›ãƒžã‚¤ã‚³ãƒ³ãƒœãƒ¼ãƒ‰ã 。RISC-Vアーã‚テクãƒãƒ£ã‚’採用ã—ãŸCH32V003ã‚’æ載ã—ã€USBケーブル1本ã§é–‹ç™ºã‚’始ã‚られる。 開発ã€è£½é€ 委託ã€å…¨æ•°æ¤œæŸ»ã€æ¢±åŒ…ã€å‡ºè·ã¾ã§ã€ã™ã¹ã¦ã‚’手ãŒã‘ã‚‹ã®ã¯åŸ‹ç”°ç¥å¸Œï¼ˆã†ã‚㟠ゆã†ã）æ°ã€ãŸã 1人。 自宅ã®æœºã®ä¸Šã§1万個を検査ã—ã€3Dプリンターã§ä½œã£ãŸæ²»å…·ã§å“質を担ä¿ã™ã‚‹ã€‚「三度ã®é£¯ã‚ˆã‚Šé–‹ç™ºãŒå¥½ãã€ã‚’ä¾¡æ ¼ã§è¡¨ç¾ã—ãŸã‚‰ã€ã™ã家ã®å®šé£Ÿã¨åŒã˜290円ã«ãªã£ãŸã€‚ ã ãŒåŸ‹ç”°æ°ã®ç›®æ¨™ã¯ã€ã“ã®ãƒœãƒ¼ãƒ‰ã§åˆ©ç›Šã‚’å¾—ã‚‹ã“ã¨ã§ã¯ãªã„ã€‚è£½é€ å·¥ç¨‹ã®ã™ã¹ã¦ã‚’オープンソース化ã—ã€ä¸–ç•Œä¸ã®èª°ã‚‚ãŒã‚¯ãƒãƒ¼ãƒ³ã§ãる状態ã«ã™ã‚‹ã“ã¨ã€‚ãã®å…ˆã«è¦‹æ®ãˆã‚‹ã®ã¯ã€Œ100å‡ã®æ£šã«ä¸¦ã‚“ã§ã„るマイコンボードã€ã 。 原価を知ã£ã¦ã„ã‚‹ã‹ã‚‰ã€è²·ãˆãªããªã£ãŸ 埋田æ°ã®æœ¬è·ã¯EMC（電ç£ä¸¡ç«‹æ€§ï¼‰ã®ã‚¨ã‚スパートã 。電å機器ãŒæ³•è¦åˆ¶ã®ç¯„囲内ã§é›»æ³¢ã‚’出ã—ã€è‡ªä»–ã¨ã‚‚ã«ãƒ‡ãƒã‚¤ã‚¹é–“ã§æ‚ª
GitHub - darklife/darkriscv: opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the DarkRISCV softcore started as an proof of concept for the opensource RISC-V instruction set. Although the code is small and crude when compared with other RISC-V implementations, the DarkRISCV has lots of impressive features: implements the UCB RISC-V RV32E and RV32I user space instruction set optional CSRs for interrupts and debu
BL702ã‚’mcuã¨ã—ã¦ä½¿ã£ã¦ã¿ã‚‹ - Qiita
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GitHub - wagiminator/CH32V003-GameConsole: Handheld RISC-V Mini Game Console with OLED Display
GitHub - YosysHQ/riscv-formal: RISC-V Formal Verification Framework
GitHub - johnwinans/riscv-toolchain-install-guide: How to download & install qemu a toolchain suitable for building and running freestanding RISC-V C/C++ programs
What is rustc? - The rustc book
GitHub - xpack-dev-tools/riscv-none-elf-gcc-xpack: A binary distribution of the GNU RISC-V Embedded GCC toolchain
GitHub - MrJake222/debug_uart: Debugging UART interface for 6502/RISC-V
GitHub - MrJake222/riscv-ice40: RISC-V survey for open-source iCE40 boards (pico-ice)
GitHub - PythonLinks/awesome-risc-v-soft-cores: Compares the different RISC-V soft cores in order to help you select the best one for your application.
GitHub - riscv/riscv-debug-spec: Working Draft of the RISC-V Debug Specification Standard
GitHub - riscv-collab/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC
GitHub - olofk/corescore: CoreScore
GitHub - splinedrive/kianRiscV: RISC-V XV6/Linux SoC, marchID: 0x2b
GitHub - stnolting/neorv32-freertos: 💾 FreeRTOS port for the NEORV32 RISC-V Processor.
Adding custom instructions in the RISC-V ISA — Adding custom instructions in the RISC-V ISA https://gitlab.com/pages/sphinx documentation
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