🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

An open-source HDL register code generator fast enough to run in real time.

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Full Stack CoffeeShop Digital Menu Cart.

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

AXI4 Verification IP

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

Utility for creating and modifying VHDL bus slave modules

Userspace I/O library for Xilinx AXI S2MM DMA

Control and status register code generator toolchain

🏄 Custom IP for vector operations

A presentation about Advanced Microcontroller Bus Architecture

FIR IP with AXI-Lite & AXI_stream

AXI DMA with Petalinux

Реализация AXI интерфейса на SystemVerilog

Code generation tool for control and status registers

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).