AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

AMBA AXI VIP

Network on Chip Implementation written in SytemVerilog

Code generation tool for control and status registers

AXI X-Bar

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Simple single-port AXI memory interface

Control and status register code generator toolchain

Xilinx PCIe to MIG DDR4 example designs and custom part data files

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

OPAE porting to Xilinx FPGA devices.

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Xilinx AXI VIP example of use

Open-Source AXI4 DMA Engine in SystemVerilog and Chisel

An open-source HDL register code generator fast enough to run in real time.

Common SystemVerilog RTL modules for RgGen

VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.