Click Bait Filter Backend (Prototype_Server)

Verilog header for easier AXI interface declaration & connection

AXI4 Verification IP

AXI DMA with Petalinux

Build an open source, extremely simple DMA.

Spotify Clone With Reactjs

AXI协议规范中文翻译版

Verilog AXI stream components for FPGA implementation

AXI 协议手册翻译

FPGA interface and driver for an OV7670 camera sensor.

Реализация AXI интерфейса на SystemVerilog

A presentation about Advanced Microcontroller Bus Architecture

VHDL UART Module with AXI interface

Full Stack CoffeeShop Digital Menu Cart.

The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure

🏄 Custom IP for vector operations

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

Сервис по подбору доступного жилья.

PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx