wishbone-bus

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Here are 27 public repositories matching this topic...

ZipCPU / zipcpu

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A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Oct 15, 2024
Verilog

ZipCPU / wb2axip

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Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

Updated Jan 12, 2024
Verilog

rggen / rggen

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Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

Updated Jul 20, 2024
Ruby

ZipCPU / wbuart32

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A simple, basic, formally verified UART controller

fpga verilog uart serialport uart-verilog wishbone verilator wishbone-bus

Updated Jan 29, 2024
Verilog

ZipCPU / sdspi

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SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

Updated Oct 15, 2024
Verilog

ZipCPU / autofpga

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A utility for Composing FPGA designs from Peripherals

c-plus-plus fpga verilog wishbone verilator wishbone-bus

Updated Jan 18, 2024
C++

ZipCPU / openarty

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An Open Source configuration of the Arty platform

fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

Updated Jan 17, 2024
Verilog

jakubcabal / uart-for-fpga

Sponsor

Star

Simple UART controller for FPGA written in VHDL

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Updated Aug 7, 2021
VHDL

ZipCPU / wbscope

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A wishbone controlled scope for FPGA's

fpga verilog debugging-tools wishbone verilator wishbone-bus

Updated Jan 12, 2024
Verilog

lxp32 / lxp32-cpu

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A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga assembly vhdl assembler risc wishbone soft-core risc-processor wishbone-bus risc-cpu

Updated Nov 2, 2024
Assembly

ZipCPU / wbi2c

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Wishbone controlled I2C controllers

fpga i2c gplv3 verilog verilator i2c-slave wishbone-bus i2c-master

Updated Feb 22, 2024
Verilog

ZipCPU / s6soc

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CMod-S6 SoC

fpga fpga-soc wishbone verilator zipcpu wishbone-bus

Updated Jan 6, 2018
Verilog

ZipCPU / dbgbus

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A collection of debugging busses developed and presented at zipcpu.com

verilog debugging-tools wishbone fgpa verilator wishbone-bus

Updated Jan 18, 2024
Verilog

ZipCPU / wbfmtx

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A wishbone controlled FM transmitter hack

fpga hack verilog wishbone verilog-components wishbone-bus fm-transmitter

Updated Jan 16, 2024
Verilog

jakubcabal / rmii-firewall-fpga

Sponsor

Star

RMII Firewall FPGA

fpga firewall vhdl ethernet wishbone-bus rmii cyc1000

Updated Dec 2, 2019
VHDL

ZipCPU / xulalx25soc

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A System on a Chip Implementation for the XuLA2-LX25 board

fpga soc zipcpu wishbone-bus

Updated Dec 13, 2018
Verilog

pbing / ibex_wb

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RISC-V Ibex core with Wishbone B4 interface

riscv systemverilog risc-v wishbone wishbone-bus

Updated Dec 24, 2019
HTML

semahawk / wishbone

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Trying to learn Wishbone by implementing few master/slave devices

verilog verilog-hdl wishbone wishbone-bus

Updated Jan 7, 2019
SystemVerilog

daniel-santos-7 / leaf

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Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

fpga riscv fpga-soc risc-v wishbone-bus processor-design

Updated Apr 23, 2023
VHDL

rlee287 / hardware-bus-infrastructure

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A collection of formal properties for hardware buses, and cores using them.

psl sva wishbone-bus axi4 axi4-lite axi4-stream bus-standards

Updated Feb 22, 2021
Verilog

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wishbone-bus

Here are 27 public repositories matching this topic...

ZipCPU / zipcpu

ZipCPU / wb2axip

rggen / rggen

ZipCPU / wbuart32

ZipCPU / sdspi

ZipCPU / autofpga

ZipCPU / openarty

jakubcabal / uart-for-fpga

ZipCPU / wbscope

lxp32 / lxp32-cpu

ZipCPU / wbi2c

ZipCPU / s6soc

ZipCPU / dbgbus

ZipCPU / wbfmtx

jakubcabal / rmii-firewall-fpga

ZipCPU / xulalx25soc

pbing / ibex_wb

semahawk / wishbone

daniel-santos-7 / leaf

rlee287 / hardware-bus-infrastructure

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