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korin id:korin

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Sinby Corp.
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korin 2015/10/07
hdl

python
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Sakai Hiroaki's Home Page
ã“ã®ãƒ›ãƒ¼ãƒ ãƒšãƒ¼ã‚¸ã¯ä»¥ä¸‹ã«ç§»å‹•ã—ã¾ã—ãŸï¼Ž ãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯ã‚’å¼µã‚Šç›´ã—ã¦ãã ã•ã„ï¼Ž ï¼•ç§’å¾Œã«è‡ªå‹•çš„ã«ç§»å‹•ã—ã¾ã™ï¼Ž http://kozos.jp/fpga/spartan3a_ether.html
korin 2007/09/16
FPGA

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HDL

Ethernet
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Monpe's Room [Design : Verilog]
æ–‡æ³•(1) : module æ–‡æ³•(2) : è«–ç†å€¤,å®šæ•°,ãƒ‡ãƒ¼ã‚¿åž‹ æ–‡æ³•(3) : å¤šbitä¿¡å·,æ¼”ç®—å æ–‡æ³•(4) : çµ„ã¿åˆã‚ã›,é †åºå›žè·¯è¨˜è¿° æ–‡æ³•(5) : ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³è¨˜è¿°(1) æ–‡æ³•(6) : ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³è¨˜è¿°(2) æ–‡æ³•(7) : ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³è¨˜è¿°(3)
korin 2007/08/16
é›»åå·¥ä½œ

verilog

hdl

fpga

cpu

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korin 2007/06/27
FPGAã«MIPSäº’æ›ãƒ—ãƒã‚»ãƒƒã‚µï¼ˆå¤–éƒ¨ãƒ¡ãƒ¢ãƒªãƒã‚¹ï¼‰ã®å®Ÿè£…

hdl
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AVM3.0 ç¶šã - ãªã¤ãŸã‚“
korin 2007/06/27
hdl
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funhdl.org
ã“ã®ãƒ‰ãƒ¡ã‚¤ãƒ³ã«ã¤ã„ã¦å•ã„åˆã‚ã›ã‚‹ funhdl.org 2023 è‘—ä½œæ¨©. ä¸è¨±è¤‡è£½ ãƒ—ãƒ©ã‚¤ãƒã‚·ãƒ¼ãƒãƒªã‚·ãƒ¼
korin 2007/06/20
hdl
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The Lava Homepage
korin 2007/06/20
hdl
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AO
Home > OpenRISC on FPGA Last modified: Apr 19, 2006 Table of Contents Abstract Hardware Software Reference Abstract OpenRISC is a 32 bit RISC CPU whose Verilog-HDL (RTL) is opened. GCC and Binutils have been ported for it. uClinux also works on it. It is distributed from OpenCores [opencores.org]. Here, I explain the way to configure OpenRISC along with the distributed tutorial. The explanation i
korin 2007/06/17
opencoresã®ã‚³ã‚¢ä½¿ã„æ–¹

HDL
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