The Reduceron
Matthew Naylor, Colin Runciman and Jason Reich Sponsored by Engineering and Physical Sciences Research Council, UK FPGA kit provided by Introduction From October 2008 to March 2010, we worked on the EPSRC-funded project The Reduceron: High-Level Symbolic Computing on FPGA. This web-page makes available the results of the project. Published material The design, implementation, and evaluation of the
Lava
sorter cmp 1 = cmp sorter cmp n = two (sorter cmp (n-1)) >-> sndList reverse >-> bfly cmp n TL;DR: The get a feel for what Lava is and how it is used to design FPGA circuits with layout skim this page and then go straight to A Sorter Example in Lava. A Hardware Description Language in Haskell Netlists in Lava Layout in Lava An Adder Example An Adder Tree in Lava A Sorter Example in Lava A 1D Systo
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Lava Tutorials
HDV: How to Use the Lava System (2010)
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