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oza_x86 id:oza_x86

FPGAã«é–¢ã™ã‚‹oza_x86ã®ãƒ–ãƒƒã‚¯ãƒžãƒ¼ã‚¯ (10)

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Altera FPGAã‚’ä½¿ã£ã¦ step by step ã§CPUã‚’ä½œã‚‹ã«ã¯? - ã±ãŸã¸ã
[fpga-cpu]ã§é¢ç™½ãã†ãªè©±é¡ŒãŒã‚ã‚Šã¾ã—ãŸã€‚ã‚³ãƒ³ãƒ”ãƒ¥ãƒ¼ã‚¿ã‚¢ãƒ¼ã‚ãƒ†ã‚¯ãƒãƒ£ã®æŽˆæ¥ã§ã€Altera FPGAã‚’ä½¿ã£ã¦ç°¡å˜ãªCPUã‚’ä½œã‚‹ã®ã§ã€ç”Ÿå¾’ã¨TAã«1å†Šã«å‹§ã‚ã‚‹ä¸€å†Šã®æœ¬ã‚’æ•™ãˆã¦æ¬²ã—ã„ã¨ã„ã†è³ªå•ã§ã™ã€‚ ã“ã®ãƒ¡ãƒ¼ãƒ«ã¸ã®ãƒªãƒ—ãƒ©ã‚¤ã«å‡ºã¦ããŸæœ¬ã¨URLã‚’ç´¹ä»‹ã—ã¾ã™ã€‚ opencoreã®ä¸ã®cpu_lecture http://opencores.org/project,cpu_lecture ä¸Šã®URLã‹ã‚‰pdfãŒãƒ€ã‚¦ãƒ³ãƒãƒ¼ãƒ‰ã§ãã¾ã™ã€‚Atmelã®8bit CPUã‚’VHDLã§å®Ÿè£…ã—ã¦ã„ã¾ã™ã€‚ã‚³ãƒ³ãƒ‘ã‚¤ãƒ©ã¯ã€æ—¢å˜ã®gcc-avrã‚’ä½¿ã£ã¦ã„ã¾ã™ã€‚ ãƒ˜ãƒãƒ‘ã‚¿ã¨ãƒ‘ã‚¿ãƒ˜ãƒ Hennesy and Peterson's Computer Architercture D.A. Patterson, J.L. Hennessy: Computer Organization & Design å®šç•ªã®2å†Šã€‚ç§ã¯ãƒ‘ã‚¿ãƒ˜ãƒ
oza_x86 2016/03/04
FPGA
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ãƒžã‚¤ã‚¯ãƒãƒ—ãƒã‚»ãƒƒã‚µã®è¨è¨ˆã¨å®Ÿè£…
æœ¬èª²é¡Œã§ã¯, ãƒ—ãƒã‚°ãƒ©ãƒ å¯èƒ½ãª LSI ã§ã‚ã‚‹ FPGA (Field Programmable Gate Array) ã‚’ç”¨ã„ã¦, ãƒžã‚¤ã‚¯ãƒãƒ—ãƒã‚»ãƒƒã‚µã®è¨è¨ˆã¨å®Ÿè£…ã‚’è¡Œã„ã¾ã™. è¨è¨ˆã«ã¯ï¼Œè«–ç† CAD ã‚’ PC ã«ã‚¤ãƒ³ã‚¹ãƒˆãƒ¼ãƒ«ã—ã¦ä½¿ã„ã¾ã™. ã“ã® CAD ä¸Šã§ä½œæˆã•ã‚ŒãŸè¨è¨ˆæƒ…å ±ã‚’ FPGA ã«ãƒ€ã‚¦ãƒ³ãƒãƒ¼ãƒ‰ã™ã‚‹ã¨, FPGA ãŒãƒ—ãƒã‚»ãƒƒã‚µã¨ã—ã¦å‹•ä½œã—, ãƒœãƒ¼ãƒ‰ãŒã‚³ãƒ³ãƒ”ãƒ¥ãƒ¼ã‚¿ã¨ã—ã¦å‹•ä½œã™ã‚‹è¨³ã§ã™ï¼Ž
oza_x86 2016/02/13
FPGA
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ãƒãƒ¼ãƒ‰ç´ äººãŒ32bit CPUã‚’FPGAã§è‡ªä½œã—ã¦å‹•ã‹ã™ã¾ã§èªã‚“ã æœ¬ã®ã¾ã¨ã‚ - ã‚¹ãƒ†ã‚£ãƒ«ãƒã‚¦ã‚¹ã®æ›¸åº«ã®æ›¸åº«
ç”·åãŸã‚‹ã‚‚ã®ä¸€åº¦ã¯è‡ªåˆ†ã§CPUã‚’ä½œã£ã¦ã¿ãŸã„ã‚‚ã®ã ã‘ã©ã€ICã§LEDã‚’ãƒ”ã‚«ãƒ”ã‚«ã•ã›ãŸç¨‹åº¦ã®çµŒé¨“ã—ã‹ãªã„ãƒãƒ¼ãƒ‰ç´ äººãªä¿ºã ã£ãŸã®ã§ã€CPUã‚’è‡ªä½œã—ã¦ã‚‹æ±å¤§ç”Ÿãªã©ã‚’é ãã‹ã‚‰è¦‹ã¦æ†§ã‚Œã¦ã‚‹ã ã‘ã ã£ãŸã€‚ã—ã‹ã—ãŠã‚ˆãä¸€å¹´å‰ã®ã“ã¨ã€ã€ŒMIPSãªã‚“ã¦ç°¡å˜ã«ä½œã‚Œã¾ã™ã‚ˆï¼ã€ã¨Kã•ã‚“ï¼ˆâ†FPGAã§Lispãƒžã‚·ãƒ³ã‚’è‡ªä½œã™ã‚‹ã‚ˆã†ãªäººï¼‰ã«è¨€ã‚ã‚Œã¦ã€ãŠã€ãŠã…ã€‚ã€‚ãã‚Šã‚ƒKã•ã‚“ã¯ãã†ã§ã—ã‚‡ã†ã‚ˆã€‚ã€‚ã‚ã‚Œã€ã‚‚ã—ã‹ã—ã¦ä¿ºã«ã‚‚ã§ãã‚‹ã‹ãªã€‚ã€‚ï¼Ÿã€€ã¨æ€ã£ãŸã€‚ã“ã®ä¸€è¨€ãŒãªã‘ã‚Œã°32bitã®CPUã‚’è‡ªä½œã—ã‚ˆã†ãªã‚“ã¦è€ƒãˆãªã‹ã£ãŸã ã‚ã†ã€‚ ãã‚Œã‹ã‚‰ä¸€å¹´ã¡ã‚‡ã„ã€ã¨ãã«ä»Šå¹´ã®æ£æœˆä¼‘ã¿ã‚„FPGA æ¸©æ³‰ã§ãŒã£ã¤ã‚ŠãŒã‚“ã°ã£ã¦ã€ãªã‚“ã¨ã‹MIPS Iã‚µãƒ–ã‚»ãƒƒãƒˆã®è‡ªä½œCPUãŒå‹•ã„ãŸã€‚ã“ã‚Œã¯ãƒ•ã‚£ãƒœãƒŠãƒƒãƒã‚’è¨ˆç®—ã—ã¦ã‚‹ã¨ã“ã‚ã€‚ ã¡ãªã¿ã«ã€ã“ã‚Œã¯ã“ã‚“ãªæ„Ÿã˜ã®ãƒ•ã‚£ãƒœãƒŠãƒƒãƒã®ã‚³ãƒ¼ãƒ‰ã‚’Cã§æ›¸ã„ã¦ã€ void main() { int i, *r = (int *)0x7f00
oza_x86 2016/02/13
FPGA
ãƒªãƒ³ã‚¯
Welcome to Bingjun's Homepage
I am a Ph.D. student in VLSI CAD Lab. My advisor is Prof. Jason Cong. I got M.S. degree in UCLA Electrical Engineering , with the Outstanding Materer Thesis Award (1 out of 104) in 2012. I got B.S. degree (with honors) in Microelectronics Department, Peking University, Beijing, China in 2010. Design novel architectures for customizable energy-efficient computing Focus on domain-specific optimizati
oza_x86 2015/11/05
FPGA
ãƒªãƒ³ã‚¯
Communication Optimization for Customizable Domain-Specific Computing
oza_x86 2015/11/05
FPGA
ãƒªãƒ³ã‚¯
https://ptopenlab.com/cloudlabconsole/
oza_x86 2015/09/22
Open Power Cloud

FPGA

Cloud

IBM
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AMD Zynqâ„¢ 7000 SoCs
Tried. Trusted. Long Lasting. With typical lifespans extending well past 15 years, you can depend on AMD devices being around for the life of your design. AMD 7 Series FPGAs and adaptive SoCs extended through 2040* AMD UltraScale+â„¢ FPGAs and adaptive SoCs extended through 2045* Read the Blog *Due to the shorter lifecycles of high-bandwidth memory (HBM) components, AMD cannot extend the lifecycle o
oza_x86 2015/09/22
Zynq

FPGA
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OpenCL meets FPGA #2 æœ€é©åŒ–ç·¨ - Qiita
ãƒ›ã‚¹ãƒˆçµŒç”±ã§å˜ãªã‚‹ã‚¢ã‚¯ã‚»ãƒ©ãƒ¬ãƒ¼ã‚¿ã¨ã—ã¦FPGAãƒœãƒ¼ãƒ‰ã‚’ä½¿ã†å ´åˆã€I/Oæ€§èƒ½ã«å¾‹é€Ÿã™ã‚‹ã‚ˆã†ãªå˜ç´”ãªã‚¿ã‚¹ã‚¯ã®ã‚¹ãƒ«ãƒ¼ãƒ—ãƒƒãƒˆå‹è² ã§ã¯ã€GPUã«å¯¾ã—ã¦ã‹ãªã‚Šåˆ†ãŒæ‚ªã„äº‹ãŒã‚ã‹ã‚Šã¾ã™ã€‚ é›»åŠ›æ€§èƒ½æ¯”ã«ã™ã‚Œã°ãƒˆãƒ³ãƒˆãƒ³ã§ã™ãŒã€ã‚³ã‚¹ãƒˆæ€§èƒ½æ¯”ãŒæ‚ªã™ãŽã¾ã™ã€‚FPGAã‚‚æ•°ãŒå‡ºã‚Œã°å®‰ããªã‚‹ã§ã—ã‚‡ã†ãŒã€ã‚³ãƒ³ã‚·ãƒ¥ãƒ¼ãƒžå‘ã‘ã«å¤§é‡ã«ãƒãƒƒãƒ—ã‚’ã°ã‚‰ã¾ã„ã¦ã„ã‚‹GPUã«æ£é¢åˆ‡ã£ã¦ç‰©é‡ã§æŒ‘ã‚€ã®ã¯ã€ç¾æ™‚ç‚¹ã§ã¯èŒ¨ã®é“ã¨è¨€ã‚ã–ã‚‹ã‚’å¾—ã¾ã›ã‚“ã€‚ ã§ã¯ã€ãƒ‡ã‚£ã‚¹ã‚¯ãƒªãƒ¼ãƒˆFPGAãŒç”Ÿãã‚‹é“ã¯ã©ã“ã‹ï¼ŸçŽ‡ç›´ã«ã„ã†ã¨ï¼š deeeeeepãªãƒ‘ã‚¤ãƒ—ãƒ©ã‚¤ãƒ³ãŒç”Ÿãã‚‹ã€Compute Intensiveãªå•é¡Œ å¤–éƒ¨I/Oã¨ç›´çµã—ã¦ãƒ¬ã‚¤ãƒ†ãƒ³ã‚·å‹è² ãƒ¡ãƒ¢ãƒªI/Oãƒãƒƒã‚¯ã«ãªã£ãŸçž¬é–“ã«è² ã‘ã‚‹ã®ã§ã€ãã‚Œä»¥å¤–ã®å ´æ‰€ã§å‹è² ã«ãªã‚Šã¾ã™ã€‚1ã¯ã¾ã‚ã€é †å½“ãªæ„Ÿã˜ã§ã™ãŒã€2ãŒè¬Žã§ã™ãã€‚å¤–éƒ¨I/Oã£ã¦ã€ä½•ã§ã—ã‚‡ã†ã‹ã€‚ ã“ã“ã¾ã§ã€æ„å›³çš„ã«ç„¡è¦–ã—ã¦ãã¾ã—ãŸãŒã€PCIe385ã«ã¯SFP+ã¨ã„ã†å…‰ã‚¤ãƒ³
oza_x86 2015/09/02
OpenCL

FPGA
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OpenCL meets FPGA #1 å…¥é–€ç·¨ - Qiita
ã‚¤ãƒ³ãƒˆãƒãƒ€ã‚¯ã‚·ãƒ§ãƒ³ OpenCLã¯ã€ãƒ˜ãƒ†ãƒã‚¸ãƒ‹ã‚¢ã‚¹ãªãƒžãƒ«ãƒã‚³ã‚¢ç’°å¢ƒã€ç‰¹ã«GPUã‚’å«ã‚€ç³»ã‚’ã‚¿ãƒ¼ã‚²ãƒƒãƒˆã¨ã—ã¦åºƒã¾ã£ã¦ããŸã¨ã„ã†å°è±¡ãŒã‚ã‚Šã¾ã™ãŒã€è¿‘å¹´ã€ãã®å‹¢åŠ›å›³ã«å¤‰åŒ–ãŒç¾ã‚Œã¤ã¤ã‚ã‚Šã¾ã™ã€‚ãƒžãƒ«ãƒã‚³ã‚¢CPUã€GPUã«ç¶šãOpenCLç•Œã®ç¬¬3å‹¢åŠ›ã€ãã‚Œã¯ãƒ»ãƒ»ãƒ» F P G Aã€‚ æœ¬è¨˜äº‹ã§ã¯ã€OpenCL for FPGAã¨ã¯ã©ã®ã‚ˆã†ãªæŠ€è¡“ãªã®ã‹ã€ãƒžãƒ«ãƒã‚³ã‚¢CPU/GPUã«æ¯”ã¹ã¦æœ¬å½“ã«ã¯ã‚„ã„ã®ã‹ãƒ»ãƒ»ãƒ»ãã®å…‰ã¨é—‡ã‚’æš´ãã€çœŸå®Ÿã‚’æ˜Žã‚‰ã‹ã«ã—ãŸã„ã¨æ€ã„ã¾ã™ã€‚ FPGAå‘ã‘OpenCLå®Ÿè£… 2014å¹´12æœˆç¾åœ¨ã€OpenCL Cè¨€èªžã‚’ç”¨ã„ã¦ãƒ‡ã‚¶ã‚¤ãƒ³ãŒå¯èƒ½ãªãƒ„ãƒ¼ãƒ«ã‚’å‡ºã—ã¦ã„ã‚‹FPGAãƒ™ãƒ³ãƒ€ãƒ¼ã¯Alteraã¨Xilinxã®2ç¤¾ã§ã™ã€‚ Altera SDK for OpenCL Xilinx SDAccel Xilinxã®SDAccelã¯å…ˆæ—¥ãƒªãƒªãƒ¼ã‚¹ã•ã‚ŒãŸã°ã‹ã‚Šã§æƒ…å ±ãŒå°‘ãªã„ãŸã‚ã€æœ¬è¨˜äº‹ã§ã¯Altera SDK fo
oza_x86 2015/09/02
FPGA

OpenCL
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Altera DE0 - Sim's blog
FIAT500ã¨æ´—è»Šã®æ—¥ã€…ãƒ»ãƒ»ãƒ»ã•ã‚“ã®è¨˜äº‹ã€ŒAltera FPGAãƒœãƒ¼ãƒ‰ DE0ã€ã§TERASICã®æ–°ã—ã„FPGAãƒœãƒ¼ãƒ‰ã®ã“ã¨ã‚’çŸ¥ã‚Šã¾ã—ãŸ(è£½å“ãƒšãƒ¼ã‚¸)ã€‚ FPGAã¯Cyclone III 3C16 FPGAã§ã€EPCS4 serial EEPROMã¨ã„ã†ã‚³ãƒ³ãƒ•ã‚£ã‚°ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ROMã‚‚æè¼‰ã•ã‚Œã¦ã„ã¾ã™ã€‚15408å€‹ã®LE(ãƒã‚¸ãƒƒã‚¯ã‚¨ãƒ¬ãƒ¡ãƒ³ãƒˆ?)ãŒæè¼‰ã•ã‚Œã¦ã„ã‚‹ã¨ã®ã“ã¨ã§ã™ãŒã€ã“ã‚Œã£ã¦ã©ã®ãã‚‰ã„å¤§ãã„ã‚‚ã®ãªã‚“ã§ã—ã‚‡ã†ã‹? $119ã¨ã‚„ãŸã‚‰å®‰ã„ä¸Šã«ã€è‰²ã€…ãªãƒšãƒªãƒ•ã‚§ãƒ©ãƒ«ãŒã¤ã„ã¦ã„ã¦ã€ãªã‹ãªã‹æ¥½ã—ãã†ãªãƒœãƒ¼ãƒ‰ã§ã™ã€‚ - 8Mãƒã‚¤ãƒˆSDR-SDRAM - 4Mãƒã‚¤ãƒˆNOR-FLASH - SDã‚«ãƒ¼ãƒ‰ã‚½ã‚±ãƒƒãƒˆ - ãƒ—ãƒƒã‚·ãƒ¥ãƒœã‚¿ãƒ³x3 - ã‚¹ãƒ©ã‚¤ãƒ‰ã‚¹ã‚¤ãƒƒãƒx10 - LEDx10 - 7ã‚»ã‚°LED 4æ¡ - 16x2LCDã‚³ãƒã‚¯ã‚¿(LCDãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¯ãªã—) - VGAå‡ºåŠ›(4096è‰²) - RS232ã‚·ãƒª
oza_x86 2009/11/05
FPGA
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1