EC8462 LIC Lab Manual

BHARATHIDASAN ENGINEERING COLLEGE.

M.G.R Nagar, K.Bandarapalli, Nattarampalli – 635 854.

(Approved by AICTE, New Delhi, Affiliated to Anna University, Chennai).
DEPARTMENT OF ELECTONICS AND COMMUNICATION ENGINEERING

LAB MANUAL
EC8462 – LINEAR INTEGRATED CIRCUITS LAB.

(Regulation – 2017)
Name : ________________________
Register Number : _________________________
Degree / Branch : B.E. / Electronics and Communication Engineering
Year / Semester : 2nd Year / 4th Semester
1
EC8462 LINEAR INTEGRATED CIRCUITS LABORATORY LTPC0032
LIST OF EXPERIMENTS
DESIGN AND TESTING OF
1. Inverting, Non inverting and differential amplifiers.

2. Integrator and Differentiator.
3. Instrumentation amplifier
4. Active low-pass, High-pass and band-pass filters.
5. Astable & Monostable multivibrators using Op-amp
6. Schmitt Trigger using op-amp.
7. Phase shift and Wien bridge oscillators using Op-amp.
8. Astable and Monostable multivibrators using NE555 Timer.
9. PLL characteristics and its use as Frequency Multiplier, Clock synchronization
10. R-2R Ladder Type D- A Converter using Op-amp.
11. DC power supply using LM317 and LM723.
12. Study of SMPS
SIMULATION USING SPICE
1. Active low-pass, High-pass and band-pass filters using Op-amp

2. Astable and Monostable multivibrators using NE555 Timer.
3. A/ D converter
4. Analog multiplier
TOTAL: 60 PERIODS
INDEX
Signature of
Exp. Date of Page
Title of the Experiment the Staff
No Experiment No
In charge
3
INVERTING AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf
+15v
R1=10K 2 7
-
IC 741
Signal
Generator + 3 + 4
6
+
Vin
~ CRO
-15v
- -
TABULATION:
Theoretical Gain Practical Gain

S.No Rf (KΩ) Vin (Volts) Vout (Volts)
A = -Rf / R1 A = V0 / Vin
1. 1K
2. 10K
3. 33K
4. 100K
MODEL GRAPH:
Vin
INPUT
Time (ms)
Vout
OUTPUT
Time (ms)
INVERTING, NON-INVERTING AND DIFFERENTIAL
AMPLIFIERS USING OP-AMP
EXP.NO: 01 DATE:
AIM:
To design the Inverting, Non-Inverting and Differential Amplifiers using Op-amp
IC741 and test their performance.
APPARATUS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY

1. IC 741 01
1KΩ, 33KΩ EACH 01
2. RESISTORS
10KΩ, 100 KΩ. EACH 02
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW
THEORY:
Op-amp in open-loop configuration has a very few application because of its
enormous open-loop gain. Controlled gain can be can be achieved by taking a part of
output signal to the input with the help of feedback. This is called as ClosedLoop
Configuration. The three basic types of closed-loop amplifier configuration are: 1.
Inverting amplifier.
2. Non-inverting amplifier.
3. Differential amplifier.
The entire configuration can be operated with either AC or DC input.
INVERTING AMPLIFIER:-
If the input signal is applied to the inverting terminal through an input resistance, a
part of output is feedback to the inverting terminal through feedback resistance Rf and
5
the non-inverting terminal grounded, then the configuration is said to be Inverting
Amplifier. It provides 1800 phase shift or polarity reversal for the given input.
Rf .
Avcl
The circuit closed-loop voltage gain is R1
NON-INVERTING AMPLIFER:-
CIRCUIT DIAGRAM:-
Rf
+15v
R1=10K 2 7
-
IC 741
+ 6
+ 3 4 +
~
Signal Vin CRO
Generator - -15v
-
TABULATION:
V in Theoretical Gain Practical Gain

S.No Rf (KΩ)
(Volts) Vout (Volts) A = 1+(Rf / R1) A = V0 / Vin
1. 1K
2. 10K
3. 33K
4. 100K
MODEL GRAPH:
Vin
INPUT
Time (ms)
OUTPUT
Vout
Time (ms)
THEORY – (NON-INVERTING AMPLIFIER):-
If the input signal is given to non inverting terminal & the feedback from output is
connected to inverting terminal of an op-amp through a potential divider network, then
it is called as Non-Inverting Amplifier Configuration. It operates in a same way as a
voltage follower (unity gain buffer), except that the output voltage is potentially
divided before it is fedback to the inverting input terminal. No phase shift or change in
the circuit closed loop polarity occurs voltage
Avcl 1 Rf
gain is R1
PROCEDURE-(INVERTING & NON-INVERTING AMPLIFIER):-

1. Select R1 as a constant value and choose a value of Rf.
2. Connect the circuit as per as the circuit diagram.
3. Apply the constant amplitude input voltage to the circuit.
4. Measure the output voltage amplitude for different value of Rf from CRO.
5. Calculate the practical gain for different value of Rf & compare it with theoretical gain.
6. Practical gain & theoretical gain should be approximately equal.

7. Plot the graph of the input wave versus output wave for any one practical case.
7
DIFFERENTIAL AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf=R2=100K
+15v
2 7
R1=10k -
IC 741
Signal
Generators + 6
R1=10K 3 4 +
+ +
~ ~ R2=100K CRO
Vin1 Vin2 -15v
TABULATION:
S. V in1 Vin2 Vin2 - Vin1 V0 Theoretical Gain Practical Gain

No (Volts) (Volts) (Volts) (Volts) A = -Rf / R1 A=V0 / (Vin2 - Vin1)
1.
2.
3.
THEORY-(DIFFERENTIAL AMPLIFIER):-
A configuration which combines inverting & non-

inverting configuration with both input terminals are supplied with Vin1 & Vin2, then it
is called as Differential Amplifier configuration. This circuit amplifies the difference
between the two inputs. Differential amplifier with a single op-amp has the exact gain of
an inverting amplifier and it is given as
Vo Rf
AD (Using One Op-Amp) AVCL
(Vin1 Vin 2 ) R1
Vo
AD (Using Two Op-Amps) AVCL 1 Rf .
(Vin 1 Vin 2 ) R1
A differential amplifier with two op-amps has the exact gain of a non-inverting amplifier and it
is given as:
PROCEDURE:
1. Select the value of R1, R2, R3 & Rf such that R1=R2 and R3=Rf.
3. Provide constant input voltage Vin1 to Non-inverting terminal of op-amp through R1 &
constant input voltage Vin2 to inverting terminal of op-amp through R2.
4. Measure the output voltage using CRO.

5. Calculate the theoretical gain and compare it with practical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.
RESULT:
Thus the Inverting, Non-Inverting and Differential Amplifiers are
designed and their performance was successfully tested using op-amp IC 741.
9
INTEGRATOR:- CIRCUIT
Cf=0.01uf
Rf=15k
+15v
R1=1.5k 2 - 7
6
Signal IC 741
Generators
+ 3 + 4 +
~
Vin
1.5K
Rcomp
-15v
RL=10k CRO
TABULATION:
Frequency Output Gain = 20 log (V 0 /Vin)
S.No (Hz) Voltage (dB)
(Volts)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODELGRAPH:
INTEGRATOR AND DIFFERENTIATOR USING OP-AMP.
EXP.NO: 02 DATE:
AIM:
To design an Integrator and Differentiator using op-amp IC 741 and to test their performance.
APPARATUS REQUIRED:

1. IC 741 --- 01
100 Ω, 1.5KΩ Each 02
2. RESISTORS
10KΩ, 15KΩ Each 01
0.1μf, 0.01μf Each 01
3. CAPACITOR
0.001μf, 05
THEORY – (INTEGRATOR):-
A circuit in which the output voltage waveform is the integral of the input voltage waveform is
the integrator or integration amplifier; Such a circuit is obtained by using basic inverting
amplifier configuration, if the feed back resistor Rf is replaced by a capacitor Cf. The Output
voltage expression is given as
1
V in dt C VO t
.
R C 1f o
1
The frequency of input at which the gain is 0 db is given as fb 2 R 1 C f
The point up to which the gain is constant & maximum is called as gain limiting frequency &
1
2 RfCf
given as fa Where Rf is the feedback resistor used to correct
the stability & roll-off problems. Between fa & fb the circuit acts as an integrator and it
is similar to a LPF. Integrator is most commonly used in analog computers, A/D
converter & signal wave shaping circuits.
Integrator as LPF (Characteristics of integrator)
Design of integrator with a lower frequency (Break Frequency) limit of integration

at fa = 1 KHz & the frequency at which 0dB results fb = 10 KHz.
11
CIRCUIT DIAGRAM: (DIFFERENTIATOR)
1. Frequency (Input)
2. Input Voltage (Vin peak)
3. Input Time Period (tVin)
4. Output Voltage (Vout peak)
5. Output Time Period (tVo)
MODEL GRAPH: SINE WAVE INPUT

PROCEDURE: (INTEGRATOR)
1. From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are calculated as
given in the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the sinusoidal input as the constant amplitude to the inverting terminal of op-amp.
4. Gradually increase the frequency & observe the output amplitude.
5. Calculate the gain with respect to frequency & plot its graph.
THEORY- (DIFFERENTIATOR):-
A differentiator or differentiation amplifier is a circuit which performs
the mathematical operation of differentiation; that is, the output waveform is the
derivative of the input waveform. The differentiator may be constructed from the basic
inverting amplifier if an input resistor R1 is replaced by capacitor C1. The
differentiation is very useful to find the rate at which a signal varies with time. For
maintaining the stability of differentiator, a series resistor R1 is connected with input
capacitor C1. the circuit will provide differentiation function but only over a limited
frequency range & over this range differentiator tend to oscillate (or) poor stability
dVin
Vo R f C1
results. The expression for output voltage is dt
PROCEDURE:
1. Select fa equal to the highest frequency of the input signal to be differentiated.
13
Calculate the component values of C1 & Rf.
2. Choose fb = 20fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of op-amp through R1
C1.
5. Observe the shape of the output signal for the given input in CRO.
6. Note down the reading and plot the graph of input versus output wave for both cases.
(ii) SQUARE WAVE INPUT
DESIGN PROCEDURE-(INTEGRATOR):-
Design of integrator to integrate at cut-off frequency 1 KHz.

1
Take fa =
2 Rf C f =
1KHz.
Always take Cf < μf and
Let
Cf =
0.01μf
1
Rf =
2 C f fa
Rf = 15.9KΩ ≡
Rf =
15KΩ
1
b
2 R1C f Take f = = 10KHz.
1
R1 2 f bC f = = 1.59KΩ.
R1 ≡
1.5KΩ
R1R f
≡ R1, Assume RL = 10KΩ
Rcomp = R1 // Rf =
R1 R f
Rcomp =
1.5KΩ
DESIGN PROCEDURE-(DIFFERENTIATOR):-
Design a differentiator to differentiate an input signal that varies in frequency
from 10Hz to 1KHz. Apply a sine wave & square wave of 2Vp-p & 1KHz frequency &
observe the output.
To find Rf & C1
Given: fa = 1KHz.
1
fa =
2 R f C1
fa = 1KHz.
15
Assume
C1 =
0.1μf
Rf = 1.59KΩ ≡
1.5KΩ
To find R1 & Cf
Select fb = 20fa with R1 C1 = Rf Cf
1
fb = 20KHz =
2 R1C1
R1 = 79.5Ω ≡
100Ω
Cf = R 1C 1 = 82X0.1X10 6
Rf 1.5K
Cf =
0.005μf.
Rom ≡ R1
// Rf = 100Ω
SINE WAVE INPUT:

Vp-p = 2V f=1KHz
Vp = 1V,
Vin = Vp sin t
= sin (2 )(103)t
dVin
Vo = -Rf c1 dt
d
= -(1.5KΩ) (0.1μf)
[sin [(2 )(103)t] dt
= -(1.5KΩ) (0.1μf) (2 ) (103) cos [(2 )(103)t]
= - 0.94 cos [(2 )(103)t]
RESULT:
Thus an Integrator and Differentiator using op-amp are designed and their performance
was successfully tested using op-amp IC 741.
17
CIRCUIT DIAGRAM:
TABULATION:
COMMON MODE GAIN CALCULATION AC
V
o
RG VI V2 Vo Ac =
S.No
(KΩ) (Volts) (Volts) (Volts) V1 V2
2
1.
2.
3.
4.
5.
INSTRUMENTATION AMPLIFIER
EXP.NO: 03 DATE:
AIM:
To construct and test the CMRR of an instrumentation amplifier using op-amp IC741.
APPARATUS REQUIRED:

1. IC 741 03
1KΩ. 06
2. RESISTORS
22KΩ 01
THEORY:
An instrumentation amplifier is the intermediate stage of a instrumentation system.

The signal source of the instrumentation amplifier is the output of the transducer.
Many transducers output do not have the ability or sufficient strength to drive the next
following stages. Therefore, instrumentation amplifiers are used to amplify the low-
level output signal of the transducer so that it can drive the following stages such as
indicator or displays.
The major requirements of a instrumentation amplifier are precise, low-level signal

amplification where low-noise, low thermal and time drifts, high input resistance &
accurate closed-loop gain, low power consumption, high CMRR & high slew rate for
superior performance.
19
DIFFERENTIAL MODE GAIN AD & CMRR CALCULATION.
V CMRR =
V1 V2 Vo
S.No RG (KΩ) Ad = o V1 Ad
(Volts) (Volts) (Volts) 20 log ( )(dB) Ac
V2
1.
2.
3.
4.
5.
PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let RG be the gain
varying resistor with different values of resistance for simplicity let RG, be a
constant value.

3. Give the input V1 & v2 to the non-inverting terminals of first & second opamp
respectively.
4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide
different input value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to calculate the
CMRR as CMRR=20 log . Ad

Ac
RESULT:
Thus an instrumentation amplifier was constructed and CMRR is
tested using op-amp IC 741.
ACTIVE LOWPASS, HIGH PASS AND BAND PASS FILTER
USING OP -AMP.
EXP.NO: 04 DATE:
AIM:
To design an Active Lowpass and Band Pass Filter using op-amp and to test their
performance
APPARATUS REQUIRED:

1. IC 741 --- 02
1.5 KΩ,22KΩ, 27KΩ EACH 02
2. RESISTORS
10KΩ 01
3. CAPACITORS 0.1μf, 0.01μf 01
THEORY – (ACTIVE LPF):-
A filter circuit which allows only low frequency range up to a higher cut-off
frequency fH is called as Low Pass Filter. An active filter uses transistor and
components such as resistor & capacitor for its design. An active filter offers the
following advantages over a passive filter.
1. Gain & frequency adjustment flexibility.

2. No loading problem because of high input impedance & low output impedance.
3. More economical because of variety of op-amps and absence of inductors.
From the frequency response, when f<fH; the gain is maximum lAl. When f=fH;
A
2
the gain is 70.7% of the maximum gain and when f fH; the gain drops or rolls
off. The frequency range from 0 to fH is called as Passband & fH to is called as
Stopband. Out of Butterworth, chebyshev & cauer filters, Butterworth filter is

21
preferred because it has flat pass band as well as flat stop band (flat-flat) filter.
LOWPASS FILTER:- CIRCUIT DIAGRAM:-
R1=27K RF=20K
+15v
2 - 7
Signal IC 741
Generator 1.5K
+ 6
3 4
+ +
Vin ~ 0.1uf
-15v
RL=10K CRO
-
TABULATION:
Frequency Output Voltage Gain = 20 log (V 0

S.No
(Hz) (Volts) /Vin) (dB)
1.
2.
3.
4.
5.
6.
7.
MODEL GRAPH:
THEORY- (ACTIVE HPF):-
An active high pass filter is simply formed by interchanging the frequency
determining resistor and capacitor in lowpass filter. A filter circuit which allows only
high frequency range greater then a lower cut-off frequency fL is called as HIGH
PASS FILTER. From the frequency response, when f<fL; the gain gradually increases
A
2
from the lowest value. When f = fL; the gain reaches 70.7% of the maximum gain
and when f > fL, the gain is maximum lAl. The frequency range
from 0 to fL is called as Stopband & fL to is called as Passband. (This is exactly
opposite to active LPF)The order of the filter tells the roll-off rate at stop band. Order
n = 1 indicates -20dB / dec (-6db / octave); Order n = 2 indicates -40dB / dec & so on.
Higher the order of the filter, better the quality will be & complex the circuit will be.
DESIGN PROCEDURE: (ACTIVE HPF):
Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same
procedure as LPF & interchange the R & C position with capacitor first & resistor in
parallel.
Vo Af ( f / fL )
In high pass filter Theoretical gain is given as =
Vin 1 ( f / fH )2
PROCEDURE - (LPF & HPF):

2. Select the corresponding cut-off frequency (higher or lower) and determine the
value of C&R. select the value of R1 & Rf depending on desired passband gain
Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of
op-amp.
4. Tabulate the output voltage Vo with respect to different values of input
frequency.
Calculate passband gain and plot the graph of frequency versus voltage gain & check the graph
to get approximately the same characteristic as shown in the model graph.
23
CIRCUIT DIAGRAM - (HIGH PASS FILTER):-
R1=27K RF=22K
+15v
2 7
-
Signal 0.1μf IC 741
Generator
+ 6
3 4 +
+
Vin ~ 1.5K -15v
RL=10K CRO
TABULATION:
Frequency Output Voltage Gain = 20 log (V 0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODEL GRAPH:
THEORY – (ACTIVE BANDPASS FILTER):-
A filter which has a pass band between two cut-off frequencies fH & fL
is called as Bandpass filter. Where fH > fL BPF is basically of two types (i) Wide
band pass filter. (ii) Narrow band pass filter.
Based on figure of merit or quality factor Q, the types are classified as follows. If Q<10,
selectivity is poor & allows higher bandwidth & such BPF is called as wide BPF.
If Q > 10, selective is more and allows only narrow bandwidth & such BPF is called
as Narrow BPF. Relationship between Q & center frequency fC is given as
fc fc
Q
BW fH fL fc fH fL
&
When frequency fL < f < fH then gain is maximum. At f < fL the gain is
gradually increasing (positive roll-off) from lower value & at f > fH the gain is gradually
decreasing (Negative roll-off) & exactly when f = fL & f = fH the gain is
A
2
70.7% of maximum gain .
PROCEDURE:
1. Select the lower and higher cut-off frequency and calculate the value of R & C
for the given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing
the HPF followed by a LPF (i.e) HPF in series with LPF.

4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of
op-amp.
5. Tabulate the output voltage Vo with respect to different values of input

frequency.
Calculate passband gain and plot the graph of frequency versus voltage gain & check the graph
to get approximately the same characteristic as shown in the model graph.
25
Frequency Output Voltage Gain = 20 log (V 0 /Vin)
S.No
(Hz) (Volts) (dB)
MODEL GRAPH:
DESIGN PROCEDURE - (ACTIVE BPF):-
Design a BPF to pass a band of 1KHz to 10KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as fH = 10 KHz and the lowest cutoff
frequency of HPF as fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
FL = ; Therefore R1 =
2 RC 2 fLC
R= ;
R = 1.59KΩ ≡
R=1.5KΩ
4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1μf. Let
C = 0.01μf.
1 1
5. Calculate R from the expression fH = ; Therefore R =
2 RC 2 fH C
R ;
R = 1.59KΩ ≡
R=1.5KΩ
6. Calculate the values of Rf & R1 with the use of

pass band gain.
BPF = 4 = 2 (HPF) X 2
Overall P.B gain of (LPF)
Therefore for both HPF & LPF the value of Rf = R1 to obtain a individual
Rf
P.B gain of 2. Af = (1+ ) = 2 (for
HPF) R1
Rf
Af = (1+ ) = 2 (for LPF)
R1
Let Rf = R1 = 22KΩ.
27
fc fc
7. Q of the filters is calculated as =
B.W fH fL
Where fC = fH fL is the center frequency.

8. Cascade HPF & then LPF to form BPF.
Calculate the practical gain dB using 20 log (Vo/Vin)
f
Vo T
fL Af ( )
And Theoretical gain is =
[1 ( f ) 2 ][1 ( f )2 ]
Vin fH fL
DESIGN PROCEDURE (ACTIVE LPF):
Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.
1. Choose the given value of fH = 1KHz.
2. Select the value of C < 1μf

1
3. Assume C = 0.1μf. Calculate R from FH =
2 RC
1
R=
2 fH C
1
R= = 1.5KΩ
3
2 X 1X 10 X 0.1 f
R = C = 0.1μf
1.5KΩ
4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + = 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ & Assume RL = 10KΩ
5. Calculate the practical gain in dB using Gain (dB)=20log (Vo/Vin);

Vo Af
Theoretical gain is given as =
Vin 1 ( f / f H )2
Af – P.B gain.
f – Input frequency.
fH – Higher cut-off frequency of LPF.
RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed and
29
CIRCUIT DIAGRAM - (ASTABLE):-
R=47K
+15v
0.01uf
2 - 7
IC 741
Vc + 6 R2=DRB
3 4
+
CRO
-
Vref R1=10K
TABULATION:
DESIGN OBSERVED VALUE

Amplitude VALUE
Waveforms
(volts) tH tL t F tH tL t F
(ms) (ms) (ms) (Hz) (ms) (ms) (ms) (Hz)
Output
waveform
Capacitive
waveform
MODEL GRAPH:
ASTABLE, MONOSTABLE MULTIVIBRATOR AND
SCHMITT TRIGGER USING OP-AMP.
EXP.NO: 05 DATE:
AIM:
To design an Astable, Monostable multivibrator and Schmitt trigger
using op-amp IC 741 and to test their characteristics.
APPARATUS REQUIRED:

1. IC 741 --- 01
100 Ω, 100KΩ, EACH 01
2. RESISTORS
10KΩ, 47KΩ, EACH 03
3. DRB (0-10)MΩ 01
4. CAPACITORS 0.01μf, 0.1μf 01
5. DIODE 1N4007 02
THEORY-(ASTABLE MULTIVIBRATOR):-
An op-amp Astable multivibrator is also called as free running oscillator. The basic principle of
generation of square wave is to force an op-amp to R2
operate in the saturation region (±Vsat). A fraction β = of the output is

R1 R2
fedback to the positive input terminal of op-amp. The charge in the capacitor increases
& decreases upto a threshold value called ±βVsat. This charge in the capacitor triggers
the op-amp to stay either at +Vsat or –Vsat. Asymmetrical square wave can also be
generated with the help of zener diodes. Astable multivibrator do not require a external
trigger pulse for its operation & output toggles from one state to another and does not
contain a stable state. Astable multivibrator are mainly used in timing applications &
waveforms generators.
DESIGN PROCEDURE:-
31
Design of square wave generator at f0 = 1 KHz.
1. The expression of fo is obtained from the charging period t1 & t2 of capacitor
1
as fo =
2 RC ln[1 (2 R1 / R2 )]
2. To simplify the above expression, the value of R1 & R2 should be taken as R2
1
o
2 RC
= 1.16R1, such that fo simplifies to f=
3. Assume the value of R1 = 10KΩ and find R2. R2 = 1.16KΩ (10K)

R2 = 11.6KΩ (DRB)
1
4. Assume the value of C & Determine R from fo =
2RC
Let C = 0.01μf
1 1
R = 2 foC = 2X(1X10 3 )(0.01X10 6 )
R = 50KΩ ≡ R =
47KΩ
5. Calculate the threshold point from
R
lVTl or lβVSATl = 1 lβVSATl where β is the feedback ratio.
R1 R2
PROCEDURE:
1. Calculate the value of components using the design procedure given.
3. As there is no specific input signal for this circuit switch ON the power supply.
4. Note down the reading for output square wave (i.e) time & amplitude and tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
TABULATION:
Amplitude Time period

S.No Waveforms
(volts) (ms)
1. Input waveform
2. Output waveform
3. Capacitive waveform
MODEL GRAPH:
INPUT
TIME (ms)
AMPLITUDE
OUTPUT
TIME (ms)
33
THEORY - (MONOSTABLE MULTIVIBRATOR):-
A multivibrator which has only one stable and the other is quasi-stable state is called
as Monostable multivibrator or one-short multivibrator. This circuit is useful for
generating single output pulse of adjustable time duration in response to a triggering
signal. The width of the output pulse depends only on the external components
connected to the op-amp. Usually a negative trigger pulse is given to make the output
switch to other state. But, it then returns to its stable state after a time interval
determined by circuit components. The pulse width T can be given as T = 0.69RC. For
Monostable operation the triggering pulse width Tp should be less then T, the pulse
width of Monostable multivibrator. This circuit is also called as time delay circuit or
gating circuit.
DESIGN PROCEDURE:
R1 10K
1. Assume R1 = R2 = 10KΩ & calculate β from expression β= =
= 0.5.
R1 R2 20K
2. Find the value of R & C from the pulse width time expression.
(1 VD /Vsat )
T = RC ln
1
(1 VD /Vsat )
T = RC ln
0.5
T ≡0.69RC.
3. Assume c = 0.01μf and R = 50KΩ ≡ 47KΩ. Find T where Rf = R3 = R
T = 0.69 (50X103) (0.01X10-6) T
= 0.345ms.
4. Triggering pulse width Tp must be much smaller than T. Tp < T.
5. Assume a HPF in the input session with C1=0.1μf (Assumption) & R4 = 100Ω.
PROCEDURE:
1. Calculate the value of components using the design procedure given.
3. Apply the negative trigger voltage to the non-inverting terminal.
4. Note down the reading for output voltage Vo & ON & OFF time period & tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
SCHMITT TRIGGER:-
CIRCUIT DIAGRAM:-
+15v
ROM=R1//R2 7
-
10KΩ IC 741
3 + 4
6
+
Vin ~ -15V RL=10K +
CRO
R2=100K -
R1
10K
TABULATION:
O/P
I/P Voltage I/P Time VUT (UTP) VLT (LTP) O/P Time
Voltage
(Volts) (ms) (Volts) (Volts) (ms)
(ms)
MODEL GRAPH:
35
THEORY-(SCHMITT TRIGGER):-
A circuit which converts a irregular shaped waveform to a square wave or pulse is

called a Schmitt trigger or squaring circuit. The input voltage Vin triggers the output
Vo every time it exceeds certain voltage levels called upper threshold voltage VUT and
lower threshold voltage VLT. The threshold voltages are obtained by using the voltage
divider. A comparator with positive feedback is said to exhibit hysteresis, a dead band
condition. The hysteresis voltage is the difference between
VUT & VLT.

There are two types of Schmitt trigger based on where the irregular wave is
given. They are, Inverting & non-inverting Schmitt trigger. Schmitt trigger finds
application in wave shaping circuits. The other name given to Schmitt trigger is
regenerativecomparator.
DESIGN PROCEDURE:-
1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity.
Let Vut = 1V & Vlt = -1V.
2. For Op-amp 741C ± Vsat ≡ ±13V to ± 14V. And assume Vref = 0, Since the another end of
R1 is grounded.
3. if Vo = +Vsat the voltage at the positive terminal will be (voltage from potential divider
R1 & R2).
Vut = Vref + R1 (Vsat - Vref )

R1 R2
Therefore Vref = 0.
Vut = R1 (+ Vsat).
R1 R2
R1
4. Similarly Vlt will be Vlt = ( ) – Vsat.
R1 R2
5. Sub Vut & assume R1 or R2 & find the other component value.
R1
1V = (13)
R1 R2
R1 + R2 = 13R1
R2 = 12R1 if R1 = 10K then R2 = 120K ≡100K.
6. Calculate ROM by
ROM = R1 // R2 = R1R2 (10K )(100K ) .

R1 R2 110K
K
1000
ROM = ≡ 10KΩ. & select RL = 10KΩ (Assumption)
110K
7. Calculate hystersis voltage Vhy = Vut – Vlt
R1
= [+Vsat – (-Vsat)]
R1 R2
K
10
= [26V] Since Vsat = 13V
110K
= 0.0909 [26V]
Vhy = 2.363V
PROCEDURE:
1. Design the value of circuit components and select VUT & VLT as given in the
design procedure.

3. Apply the input signal to the input terminal of op-amp & set VUT & VLT values.
4. Note down the readings from the output waveform.

5. Plot the graph & show the relationship between Input sine wave & Output square wave.
RESULT:
Thus an Astable, Monostable multivibrator and Schmitt trigger are
designed and tested using op-amp IC 741.
37
RC PHASE SHIFT OSCILLATOR
-
Exp. No : 6 Date:
AIM:
To design RC Phase Shift and Wien Bridge Oscillator using op-amp IC 741 and
to test its performance.
APPARATUS REQUIRED:

1. IC 741 --- 01
1.5KΩ 3.3KΩ, 33KΩ, EACH 03
2. RESISTORS 10 KΩ 22 KΩ, 1MΩ, EACH 01
3. CAPACITORS 0.1μf 03
THEORY:
RC phase shift oscillator produces 360° of phase shift in two parts. Firstly, each and
every RC pair in the feedback network produces 60° phase shift and totally there were
three pairs, thus producing 180° Phase shift and secondly, the feedback input is given
to the inverting terminal of op- amp to produce another 180° phase shift
and a total phase shift of 360°.
The frequency of oscillation is given by f0 = 1 ; If an inverting
2 6RC
amplifier is used, the gain must be atleast equal to 29 to ensure the oscillations with constant
amplitude that is, A < 1. Otherwise
V
the oscillation will die out.
DESIGN PROCEDURE:
Design a RC phase shift oscillator to oscillate at 200Hz.
1.
Select fo = 200Hz.
2.
Assume C = 0.1μf & determine R from fo.
1 1
fo = = R = = 3.3K.
2 6RC 2 6 foc
3.
To prevent the loading of amp because it is necessary that R1>>10R. Therefore
R1=10R=33K.
4.
At this frequency the gain must be atleast 29 (i.e)Rf / R1 =29.
Therefore Rf = 29R1.
RC PHASE SHIFT OSCILLATOR:-
CIRCUIT DIAGRAM:-
OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period
(volts) Frequency (Hz) (Hz)
(ms)
MODEL GRAPH:
Vout
Time (ms)
OUTPUT
39
Rf = 29 (33K) = 957KΩ. Therefore use Rf = 1MΩ.
WIEN BRIDGE OSCILLATOR:-

CIRCUIT DIAGRAM:-
R1=10K Rf=22K
+15v
2 - 7
IC 741
3 + 4
6
R=1.5K C=0.1uf
-15v +
CRO
R=1.5K -
C=0.1uf
TABULATION:
OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period
(volts) Frequency (Hz) (Hz)
(ms)
MODEL GRAPH:
Vout
Time (ms)
OUTPUT PROCEDURE- (RC
PHASE SHIFT):-
1. Select the given frequency of oscillation f0 =
200Hz.
1 2.
Assume either R or C to find out the other using formula f0 = .
2 6R
C
3. The gain is selected such that Rf / R1 = 29K. Assume Rf or R1 to find the other.
5. Measure the amplitude frequency of the output signal plot the graph.
THEORY – (WIEN BRIDGE):-
A bridge circuit with two components connected in series and parallel combination is
used to archived the required of phase shift of 00. When the bridge is balanced the
phase shift of 00 is achieved and the feedback signal is connected to the positive
terminal; of Op-amp. So the Op-amp is acting as a non-inverting amplifier and the
feedback network do not provide any phase shift.
The major drawback of wien bridge oscillator is difficulty in balancing the bridge
circuit. This occurs because of drift in component values due to external
nd internal
disturbanc
es. The
frequency
of
oscillation
is given as
f0 = .
C
DESIGN PROCEDURE:
(i) Select frequency f0 = 1KHz.

1
(ii) Use f0 = , A = 1+(Rf / R1) = 3. To find R & Rf.
2 RC
(iii) Therefore Rf = 2R1 & assume C = 0.1μf & find R from
1
R= = 1.59KΩ.
2 foC
(iv) Assume R1 = 10K & find Rf from Rf = 2R1
Therefore Rf = 20K ≡ 22KΩ
PROCEDURE:
Select the given frequency of oscillation f0 = 1 KHz.
1.
1
2.
Assume either R or C to find out the other using formula . Also
41
2 RC
determine the value of other components as given in design procedure.
3.
Connect the circuit as per as the circuit diagram.
4.
Measure the amplitude and frequency of the output signal to plot the graph.
RESULT:
Thus RC Phase Shift and Wien Bridge Oscillator were designed and
PIN CONFIGURATION OF 555 TIMER IC
Features of 555 IC:-

1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or between pin 3
& VCC (supply)
2. 555 can be reset by applying negative pulse, otherwise reset can be connected to +Vcc to
avoid false triggering.
3. An external voltage effects threshold and trigger voltages.
4. Timing from micro seconds through hours.
5. Monostable and bistable operation
6. Adjustable duty cycle
7. Output compatible with CMOS, DTL, TTL
8. High current output sink or source 200mA
9. High temperature stability
10. Trigger and reset inputs are logic compatible.
Specifications:-
1. Operating temperature : SE 555-- -55oC to 125oC
NE 555-- 0o to 70oC
2. Supply voltage : +5V to +18V
3. Timing : μSec to Hours
4. Sink current : 200mA
5. Temperature stability : 50 PPM/oC change in temp or 0-005% /oC.
Applications:-
1. Monostable and Astable Multivibrator
2. dc-ac converters
3. Digital logic probes
4. Waveform generators
5. Analog frequency meters
6. Tachometers
7. Temperature measurement and control
8. Infrared transmitters
9. Regulator & Taxi gas alarms etc.
43
Block Diagram of IC 555:
Function of Various Pins

of 555 IC:
Pin (1) of 555 is the ground terminal; all voltages r measured with respect to this pin.
Pin (2) of 555 is the trigger terminal, If the voltage at this terminal is held greater than
one-third of VCC, the output remains low. A negative going pulse from Vcc to less than
Vec/3 triggers the output to go high. The amplitude of the pulse should be able to
make the comparator (inside the IC) change its state. However the width of the
negative going pulse must not be greater than the width of the expected output pulse.
Pin (3) is the output terminal of IC 555. There are 2 possible output states. In the low
output state, the output resistance appearing at pin (3) is very low (approximately
10 Ω). As a result the output current will goes to zero , if the load is connected from
Pin (3) to ground , sink a current I Sink (depending upon load) if the load is connected
from Pin (3) to ground, and sinks zero current if the load is connected between +VCC
and Pin (3).
Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the
potential of Pin (4) is drives below 0.4V, output is immediately forced to low state.
The reset terminal enables the timer over-ride command signals at Pin (2) of the IC.
Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels at
which the time comparators change state. A resistor connected from Pin (5) to ground
can do the job. Normally 0.01μF capacitor is connected from Pin (5) to ground. This
capacitor bypasses supply noise and does not allow it affect the threshold voltages.
Pin (6) is the threshold terminal. In both Astable as well as Monostable modes, a
capacitor is connected from Pin (6) to ground. Pin (6) monitors the voltage across the
capacitor when it charges from the supply and forces the already high O/p to Low
when the capacitor reaches +2/3 VCC.
Pin (7) is the discharge terminal. It presents an almost open circuit when the output is
high and allows the capacitor charge from the supply through an external resistor and
presents an almost short circuit when the output is low.
Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V.
45
CIRCUIT DIAGRAM - (ASTABLE):
TABULATION:
DESIGN VALUE OBSERVED VALUE

Amplitude
Waveforms
(volts) tH tL t F tH tL t F
(ms) (ms) (ms) (Hz) (ms) (ms) (ms) (Hz)
Output
waveform
Capacitor
waveform
(Capacitor
voltage Vc)
ASTABLE & MONOSTABLE MULTIVIBRATOR
USING IC 555 TIMER.
EXP.NO: 07 DATE:
AIM:
To Design and test Astable and Monostable multivibrator using 555 timer IC.
APPARATUS REQUIRED:

1. IC 555 --- 01
2. RESISTORS 3.3KΩ,6.8KΩ,10KΩ. EACH 01

3. CAPACITORS 0.1μf, 0.01μf. EACH01
THEORY:
When the power supply VCC is connected, the external timing capacitor „C” charges
towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high
(≈VCC) as Reset R=0, Set S=1 and this combination makes Q = 0 which has unclamped the
timing capacitor „C‟.
When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the
control flip flop on that Q=1. It makes Q1 ON and capacitor „C‟ starts discharging
towards ground through RB and transistor Q1 with a time constant RBC. Current also
flows into Q1 through RA. Resistors RA and RB must be large enough to limit this
current and prevent damage to the discharge transistor Q1. The minimum value of RA
is approximately equal to VCC/0.2 where 0.2A is the maximum current through the ON
transistor Q1.
During the discharge of the timing capacitor C, as it reaches VCC/3, the lower
comparator is triggered and at this stage S=1, R=0 which turns Q=0. Now Q=0
unclamps the external timing capacitor C. The capacitor C is thus periodically
charged and discharged between 2/3 VCC and 1/3 VCC respectively. The length of time
that the output remains HIGH is the time for the capacitor to charge from 1/3
47
VCC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of VCC
volts is given by VC = VCC [1- exp (-t/RC)] Total time period T = 0.69 (RA + 2 RB) C
f = 1/T = 1.44/ (RA + 2RB) C
MODEL GRAPH:
(a): Square wave output

(b): Capacitor voltage of Square wave output
DESIGN PROCEDURE:-
Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 30%
using 555 timer IC. Given Frequency=1000Hz
Duty cycle=30%
D= T low/T high = RB/RA+2RB*100 -----------------------------------(1)
T high =0.69(RA+RB)C
T low = 0.69 RBC
From equation 1
0.30 T high = T low
0.30 * 0.69(RA+RB)C = 0.69 RBC
0.201(RA+RB)C = 0.69 RBC
0.483 RB-0.207 RA= 0 -----------------------------------------------(2)
given f=1khz we know that T=1/f
T=1ms
T= T high + T low
0.69(RA+RB)C +0.69 RBC= 1ms.
0. 69(RA+RB) +0.69 RB = 1ms./C
Let C=0.1μF
0.69RA+0.69RB +0.69 RB = 1ms./0.1*10-6
0.69RA+1.38RB = 10 4 ------------------------------------------------(3)
Solving equation 2 & 3 we get

RA=6.8K
RB= 2.674K ≡3.3KΩ
Procedure:
1. Calculate the component values using the design procedure.
3. Observe and note down the output waveform.
4. Measure the frequency of oscillations and duty cycle and then compare with the given
values.
5. Plot both the waveforms to the same time scale in a graph.

THEORY- (MONOSATBLE):-
A Monostable Multivibrator, often called a one-shot Multivibrator, is a
pulsegenerating circuit in which the duration of the pulse is determined by the RC
network connected externally to the 555 timer. In a stable or stand by mode the output
of the circuit is approximately Zero or at logic-low level. When an external trigger
pulse is given, the output is forced to go high ( VCC). The time for which the output
remains high is determined by the external RC network connected to the timer. At the
end of the timing interval, the output automatically reverts back to its logic-low stable
state.
The output stays low until the trigger pulse is again applied. Then the cycle repeats.
49
The Monostable circuit has only one stable state (output low), hence the name Monostable.
Normally the output of the Monostable Multivibrator is low.
DESIGN PROCEDURE:-
Let, RA = 10K
Out put pulse width tp = 10μs
tp=1.1RAC
C= 0.909μF
C=0.1μF
PROCEDURE:-
1. Calculate the value of R & C using design procedure.
3. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
4. Observe the output waveform and measure the pulse duration.
5. Theoretically calculate the pulse duration as Thigh=1.1 RAC
MONOSTABLE MULTIVIBRATOR:-
CIRCUIT DIAGRAM:-
Amplitude Time period

S.No Waveforms
(volts) (ms)
1. Input waveform
2. Output waveform
Capacitive waveform
3.
(Capacitor voltage Vc)
MODEL GRAPH:
RESULT:
Thus the Astable and Monostable multivibrator is designed and tested using
555 timer IC
51
Pin Configuration:
Specifications:
1. Operating frequency range : 0.001 Hz to 500 KHz
2. Operating voltage range : ±6 to ±12V
3. Inputs level required for tracking max. : 10mV rms minimum to 3v (p-p)
4. Input impedance : 10 KΩ typically

5. Output sink current : 1mA typically
6. Drift in VCO center frequency : 300 PPM/oC typically
(fout) with temperature
7. Drif in VCO centre frequency with supply: 1.5%/V maximum
voltage
8. Triangle wave amplitude : typically 2.4 VPP at ± 6V
9. Square wave amplitude : typically 5.4 VPP at ± 6V
10. Output source current : 10mA typically
11. Bandwidth adjustment range : <±1 to >± 60%
Center frequency fout = 1.2/4R1C1 Hz
= free running frequency
FL = ± 8 fout/V Hz
V = (+V) – (-V)
fL
2 (3.6) x10 3 xC 2 1/ 2
fc = ±
Applications:
1. Frequency multiplier
2. Frequency shift keying (FSK) demodulator
3. FM detector
PLL IC 565
THEORY:-
The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE
560, 561, 562, 564, 565, & 567 differ mainly in operating frequency range, power
supply requirements and frequency and bandwidth adjustment ranges. The device is
available as 14 Pin DIP package and as 10-pin metal can package. Phase comparator
or phase detector compare the frequency of input signal fs with frequency of VCO
output fo and it generates a signal which is function of difference between the phase of
input signal and phase of feedback signal which is basically a d.c voltage mixed with
high frequency noise. LPF remove high frequency noise voltage. Output is error
voltage. If control voltage of VCO is 0, then frequency is center frequency (fo) and
mode is free running mode. Application of control voltage shifts the output frequency
of VCO from fo to f. On application of error voltage, difference between fs & f tends
to decrease and VCO is said to be locked. While in locked condition, the PLL tracks
the changes of frequency of input signal.
Block Diagram of IC 565
53
PROCEDURE:
1. Determine the component values using the design procedure given here.
2. Connect the components as shown in the circuit diagram.
3. Note down the readings of output waveform with respect to input signal.
CIRCUIT DIAGRAM:
NE 565 PLL connection diagram
DESIGN PROCEDURE:-
If C= 0.01μF and the frequency of input trigger signal is 2KHz, output pulse
width of 555 in Monostable mode is given by
1.1RAC = 1.2T =1.2/f
RA= 1.2/(1.1Cf)=54.5KΩ
fIN=fOUT/N
Under locked conditions,
fOUT = NfIN = 2fIN = 4KHz
PLL CHARACTERISTICS AND FREQUENCY
MULTIPLIER USING PLL
EXP.NO: 08 DATE:
AIM:
To design & test the characteristics of PLL and to construct and test frequency
multiplier using PLL IC565.
APPARATUS REQUIRED:
S.NO COMPONENT VALUE QUANTITY
1 IC 565 --- 01
2 IC 555 --- 01
12KΩ, 54.5 KΩ,

3 RESISTORS Each one
6.8K
0.01μF 4
CAPACITORS
4
0.1 μf, 10μf, 1 μf EACH 01
5 DIGITAL TRAINER KIT --- 01
6 REGULATED POWER SUPPLY (0 -30V), 1A 1
7 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1
8 CONNECTING WIRES --- FEW
55
PLL as Frequency Multiplier
(a): Input
(b): PLL output under locked conditions without 555
(c): Output at pin4 of 565 with 555 connected in the feedback
Theory:
The frequency divider is inserted between the VCO and the phase
comparator of PLL. Since the output of the divider is locked to the input frequency f IN,
the VCO is actually running at a multiple of the input frequency .The desired amount
of multiplication can be obtained by selecting a proper divide– by – N network ,where
N is an integer. To obtain the output frequency fOUT=2fIN, N = 2 is chosen. One must
determine the input frequency range and then adjust the free running frequency fOUT of
the VCO by means of R1 and C1 so that the output frequency of the divider is midway
within the predetermined input frequency range. The output of the VCO now should
be 2fIN . The output of the VCO should be adjusted by varying potentiometer R1. A
small capacitor is connected between pin7 and pin8 to eliminate possible oscillations.
Also, capacitor C2 should be large enough to stabilize the VCO frequency.
SAMPLE READINGS:
PARAMETER INPUT OUTPUT
Amplitude (Vp-p)
Frequency (KHz)
PROCEDURE:-
1. The circuit is connected as per the circuit diagram.
2. Apply a square wave input to the pin2 of the 565 3.
Observe the output at pin4 of 565 under locked condition.
4. Give the output of 565 to the pin2 of 555 IC.

5. Observe the output of 555 at pin3.
6. Now give the output of 555 as feedback to the pin5 of the 565.
7. Observe the frequency of output signal fo at pin4 of 565 IC.
8. Plot the waveforms in graph.
RESULT:
Thus the PLL characteristics are designed and tested and Frequency multiplier using
IC 565 is constructed and tested.
57
PIN DIAGRAM:
CIRCUIT DIAGRAM - (LM723):
Vin (0-30) V
HI
Vref=5V HI
12 11
R4=100E
6 10
R1=1K
IC 723 2
5
R2=3.3K 3
R3=30E
7
13 4
C=220pf
Vo
DC POWER SUPPLY USING LM317 AND LM723.
EXP.NO: 09 DATE:
AIM:
To design and test the power supply voltage regulator using LM317 and
LM723
APPARATUS REQUIRED:
1. LM317 and LM723 --- EACH 01
30 Ω, 100Ω, 1KΩ,
2. RESISTORS EACH 01
3.3KΩ, 220Ω,
4. ANALOG VOLTMETER (0-10)V 01
5. DUAL POWER SUPPLY (0-30)V 01
THEORY:
A voltage regulator is a circuit that supplies a constant voltage regardless of
changes in load current and input voltage variations. Using IC 723, we can design
both low voltage and high voltage regulators with adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of voltages Vo <
Vref, where as for high voltage regulator, it is VO > Vref. The voltage Vref is generally
about 7.5V. Although voltage regulators can be designed using Opamps, it is quicker
and easier to use IC voltage Regulators.
IC 723 is a general purpose regulator and is a 14-pin IC with internal short circuit
current limiting, thermal shutdown, current/voltage boosting etc. Furthermore it is an
adjustable voltage regulator which can be varied over both positive and negative
voltage ranges. By simply varying the connections made externally, we can operate
the IC in the required mode of operation. Typical performance parameters are line and
load regulations which determine the precise characteristics of a regulator
59
TABULATION:
INPUT VOLTAGE OUTPUT VOLTAGE

S.NO
(Volts) (Volts)
1.
2.
3.
4.
5.
6.
7.
8.
MODEL GRAPH:
CHARACTERISTICS OF THE LM317HVK:
The LM317HVK will provide a regulated output current of upto

1.5A,Provided that if is not subjected to a power dissipation of more than about
15W.This means it should be electrically isolated from, and fastened to, a large heat
sink such as the metal chassis of the power supply.
The LM317 requires a minimum “dropout” voltage of 3v across its input and
output terminals or it will drop out of regulation. Thus the upper limit of Vo is 3V
below the minimum input voltage from the unregulated supply.
It is good practice to connect bypass capacitors .This reduces the ripple voltage from the
rectifier.
The LM317HVK protects itself against over heating, too much internal power
dissipation and too much current. When the chip temperature reaches 175 degrees, the
317 shuts down. If the product of output current and input-to-output voltage exceeds
15 to 20W, or if currents greater than about 1.5A are required the LM317 also shuts
down. When the overload condition is removed the Operation is resumed. All these
features are made possible by the remarkable internal circuitry of LM317.
Along with the simple 3 pin fixed regulators; a number of adjustable or

programmable devices are available. Some devices also include features such as
programmable current limiting. It is also possible to configure multiple regulators so
that they track or follow each other.
DESIGN PROCEDURE: (IC723)

Given :
Vref =5v
Vo=4v
We know that
Vo=Vref(R2/(R1+R2))
4R1+4R2=5R2
R2=4R1
Let R1=1k
R2=4K ≡3.3KΩ
61
PIN DIAGRAM:
CIRCUIT DIAGRAM - (LM317):
MODEL GRAPH:
TABULATION:
INPUT VOLTAGE OUTPUT VOLTAGE

S.NO
(Volts) (Volts)
PROCEDURE:
1) Connections are made as per the circuit diagram.
2) The reference voltage of 5v is set and the input voltage is varied between (0-30) v 3) The
corresponding output is taken using voltmeter.
4) The readings are tabulated and the graph is plotted.
RESULT:
The 723 & 317 voltage regulators are designed and the regulation of supply voltage was
tested.
63
PIN DETAILS:
PIN NO. FUNCTION
1 Inverting input
2 Non Inverting input
3 Oscillator output
4 (+)CL sense
5 (-)CL sense
6 RT
7 CT
8 Ground(-ve supply voltage)
9 Compensation
10 Shutdown
11 Emitter-A
12 Collector-A
13 Collector-B
14 Emitter-B
15 Vin
16 Vref
TECHNICAL INFROMATION:
TEMPERATURE
DESCRIPTION
RANGE
SG3524N(16-pin plastic DIP) 0 C to 70 C
SG3524F(16-pin cerdip) 0 C to 70 C
SG3524D(16-pin SO) 0 C to 70 C
STUDY OF SMPS
EXP.NO: 10 DATE:
AIM:
To study the control of SMPS
THEORY:
The switching regulator is also called as switched mode regulator. In this case, the
pass transistor is used as a controlled switch and is operated at either cutoff or
saturated state. Hence the power transmitted across the pass device is in discrete pulses
rather than as a steady current flow. Greater efficiency is achieved since the pass
device is operated as a low impedance switch. When the pass device is at cutoff, there
is no current and dissipated power. Again when the pass device is in saturation, a
negligible voltage drop appears across it and thus dissipates only a small amount of
average power, providing maximum current to the load. The efficiency is switched
mode power supply is in the range of 70-90%.
A switching power supply is shown in figure. The bridge rectifier and capacitor
filters are connected directly to the ac line to give unregulated dc input. The reference
regulator is a series pass regulator. Its output serves as a power supply voltage for all
other circuits. The transistors Q1, Q2 are alternatively switched „on‟ &; off, these
transistors are either fully „on‟ or „cut-off, so they dissipate very little power. These
transistors drive the primary of the main transformer. The secondary is centre tapped
and full wave rectification is achieved by diodes D1 and D2. This unidirectional
square wave is next filtered through a two stage LC filter to produce output voltage
Vo.
SG 3524: FUNCTION:
Switched Mode Power Supply Control Circuit
FEATURES:
Complete PWM Power Controlled circuitry.
Single ended or push-pull outputs.
Line and Load regulation of 0.2%.
1% maximum temperature variation.
Total Supply current is less than 10mA
Operation beyond 100KHz
RESULT:
Thus the control of SMPS IC SG3524 had been studied.
65
Instrumentation Amplifier:
VEE1 0 5
VCC1 4 VCC2 9 0 DC 15
.TRAN 0 VEE2 0 10 DC 15 20MS
.OP
4 0 DC 15
.PROBE .END
Lowpass VEE3 0 15 DC 15 Filter:
V1 7 0 SIN(0 5V 100)
V2 1 0 SIN(0 3V 100)
R1 3 2 1K
R2 8 6 1K
R3 2 6 500
R4 3 11 1K
R5 8 12 1K
RF 11 13 1K
R6 12 0 1K
X1 1 2 4 5 3 UA741
X2 7 6 9 10 8 UA741
X3 12 11 14 15 13 UA741
VIN 2 AC 4
R1 1 0 22K
R2 1 4 22K
R3 2 3 1.5K
RL 4 0 10K
67
C1 3 0 0.1U
X1 3 1 5 6 4 UA741
.AC DEC 10 10 1MEG
.OP
.PROBE .END Highpass Filter:
VIN 2 AC 4
R1 1 0 22K
R2 1 4 22K
C1 2 3 0.1U
0 10K
R3 3 0 1.5K
X1 3 1 5 6 4 UA741
.AC DEC 10 10 100K
.OP
.PROBE .END Active Bandpass Filter:
68
VCC1 10 DC 15
VEE1 0 11 DC 15
VIN 2 0 AC 4
R1 1 0 22K
R2 1 4 22K
R3 3 0 1.5K
R4 4 7 1.5K
R5 8 0 22K
R6 8 9 22K
RL 9 0 10K
C1 2 3 0.1U
C2 7 0 0.01U
X1 3 1 5 6 4 UA741
X2 7 8 10 11 9 UA741
.AC DEC 10 10 10MEG
.OP
.PROBE .END Astable Multivibrator:
4
0 5
R1 2 0 10K
R2 2 3 11.6K
R3 1 3 50K
C1 1 0 0.01U
69
X1 2 1 4 5 3 UA741
.TRAN 0 5MS UIC
.OP
.PROBE
.END
Monostable Multivibrator:
6
0 7
VIN 4 0 PULSE(4 0 1MS 0.001MS 0.001MS 1MS 2MS)
R1 5 2 10K
R2 2 0 10K
R3 1 5 50K
R4 3 0 100
C1 4 3 0.1U
C2 0 1 0.1U
D1 1 0 D1N4148
70
D2 2 3 D1N4148
X1 2 1 6 7 5 UA741
.TRAN 0 20MS
.OP
PROBE .
END
Schmitt Trigger:
.LIB.EVAL.LIB
VCC 5 0
VEE 0 6
VIN 1 0 SIN(0 4 100)
R1 3 0 10K
R2 3 4 100K
R3 1 2 10K
RL 4 0 10K
X1 3 2 5 6 4 UA741
.TRAN 0 30MS
.OP
.PROBE
.END
71
RC Phase shift Oscillator:
Program:
.LIB EVAL.LIB
VCC 7 0
VEE 0 8 DC 15
72
IS 3 0 PWL(0US 0MA 10US 0.1MA 40US 0.1
MA
50US 0MA 10MS 0MA)
R1 1 2 33K
R2 2 4 1.02MEG
R3 5 0 3.3K
R4 6 0 3.3K
R5 1 0 3.3K
R6 3 0 33K
C1 5 4 0.1U
C2 6 5 0.1U
C3 1 6 0.1U
X1 3 2 7 8 4 UA741
.TRAN 0 1
.OP
.PROBE
.END
Wein Bridge Oscillator:
Program:
.LIB EVAL.LIB
VCC 5 0
73
VEE 0 6 DC 15
IS 2 0 PWL(0US 0MA 10US 0.1MA 40US 0.1
MA
50US 0MA 10MS 0MA)
R1 1 0 15K
R2 1 4 30.2K
R3 2 3 1.5K
R4 2 0 1.5K
C1 3 4 0.1U
C2 2 0 0.1U
X1 2 1 5 6 4 UA741
.TRAN 0 1
.OP
.PROBE
.END
ADDITIONAL
EXPERIMENTS
74
EQUIVALENT BINARY
PRACTICAL THEORTICAL
DECIMAL
bo b1 b2 b3 VOLTAGE VOLTAGE
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
75
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
76
DIGITAL TO ANALOG CONVERTER USING IC 741 OP-AMP
EXP.NO: 12 DATE:
AIM:
To design and test the operation of a 4 bit R – 2R ladder type digital to analog
converter using op-amp IC 741.
APPARATUS REQUIRED:

1. IC 741 --- 01
10 KΩ 03
2. RESISTORS
22KΩ 06
4. VOLTMETER (0-10)V 01
5. CONNECTING WIRES --- Few
THEORY:
Most DACs architectures are based on the popular R-2R ladder. Starting from the
left hand side of the circuit to the right hand side, one can easily prove that the equivalent
resistance to the right of each labeled node equals 2R. Consequently, the current flowing
downward, away from each node equal to the current flowing toward the right; twice this
current enters the node from the left. The currents and, hence, the node voltages are binary
weighted.
With a resistance spread of only 2-to-1, R-2R ladders can be fabricated

monolithically to a high degree of accuracy and stability. Depending on how ladders are
used, there were many DAC architectures available. There were two common types of R-
2R DACs available based on current or voltage.
They are Current mode DAC and Voltage mode DAC based on whether the circuit
operated on current or voltage respectively. The major advantage of R-2R ladder
architecture when compared with the binary weighted type is the use of only two value
resistors. These two values R and 2R make the design simple for any resolution and thus
easily realizable as an integrated circuit.
MODEL GRAPH:
77
0 0 1 1 0 1 1
0 0 0 0 1 1 1
0 0 0 0 1 1 1 Binary I/P
O/P VOLTAGE
0 1 0 1 1 0 1
(V)
DESIGN PROCEDURE:
1. Assume any value of R & find 2R.
2. Let R = 10KΩ; therefore 2R = 20KΩ ≡ 22KΩ.
3. Let Rf = 2R = 22KΩ.
PROCEDURE:
1. Select the given resolution as 24 = 16.
2. Assume the value of Resistor R and thus select another resistor with twice a value of the
first resistor (2R).
3. Connect the circuit as shown in the circuit diagram. Connect the series resistances R
finally to the inverting terminal of the op-amp.
4. Connect the other end of the parallel arm resistors 2R to the digital switch to represent
binary logic conditions.
5. Calculate the output voltage from the voltmeter. Since negative output results from op-
amp connect the output of op-amp to the negative terminal of the voltmeter, to get
Positive deflections.
6. Plot the graph for output voltage versus input binary combinations.
78
RESULT:
Thus the R – 2R ladder type digital to analog converter is designed & tested using
op-amp IC 741.
79
SAMPLE VIVA-VOCE QUESTIONS & ANSWERS
SAMPLE VIVA-VOCE QUESTIONS AND ANSWERS EXPT
NO.1:
INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIERS

USING OP-AMP
1. Define operational amplifier

Ans: Op-amp is an operational amplifier capable of performing mathematical
operations such as addition, subtraction, multiplication, logarithm, anti-logarithm,
integration, differentiation etc and amplification. It is a multi stage differential amplifier
which is in wide variety of applications.
2. What is the difference between ordinary amplifier and operational amplifier?

Ans: An ordinary amplifier can only amplify the given input signal. But, an
operational amplifier can perform many mathematical operations with enormous gain.
3. What are the different types of op-amp configurations available?

Ans: Op-amp configurations are broadly subdivided into two types. They are open-
loop and Closed-loop configurations. Open loop configurations are of three types. They are
Inverting, Non-inverting and differential configuration. Closed-loop configurations are of
three types. They are Inverting, Non-inverting, buffer amplifier and differential
configuration. The differential configuration of closed-loop op-amp is further subdivided
into two types. They are configuration with one op-amp and configuration with two op-
amps.
4. Which is the basic building block of operational amplifier?

Ans: The basic building block of op-amp is differential amplifier. A differential
amplifier amplifies the difference between two input signals.
5. Mention some of the applications of op-amp.

Ans: Op-amps are mainly used in analog system design. They are used for wide
variety of applications such as mathematical operations, data acquisition systems, process
control, programmable gain amplifiers, automotive instrumentation and control,
communication ICs, radio/audio/video ICs, analog computers, A/D converters etc.
6. Can an op-amp be used for both AC and DC Applications?
80
Ans: Yes. Op-amps can be used for both AC and DC applications. This is one of the
important features of an op-amp. They have the ability to process both AC and DC input
signals.
7. Why negative feedback is preferred in op-amp?

Ans: In most of the op-amp application, negative feedback is preferred to decrease
the overall voltage gain. Open-loop gain is huge and this is minimized by using two
resistors. Input resistor and feedback resistor is used to control the gain and thus suitable
for many practical applications.
8. List out the ideal characteristics of op-amp.

Ans: The ideal characteristics of op-amp are
i) Open-loop gain must be infinite. AoL = ∞ ii) The input impedance must
be infinite. Ri = ∞ iii) The output impedance must be zero. Ro = 0 iv)
Common Mode Rejection Ratio must be infinite. CMRR = ∞ v) Slew rate
must be infinite. dvo/dt = ∞ vi) It must not provide output when there is no
input. Vo = 0; when Vi = 0.
vii) Differential mode gain must be infinite. Ad = ∞
viii) Common mode gain must be zero. Ac = 0
9. Define slew rate. What causes it? Mention the effects and methods of minimizing
Slew rate.
Ans: It is the rate at which the output voltage changes with respect to time. It tells
how fast an output of op-amp can change. Example: For a general purpose op-amp
741, the maximum slew rate is 0.5V/µs. This means, the output voltage can change a
maximum of 0.5V in 1 µs. Slew rate is a major limiting factor for op-amps operating at
high frequency.
Slew rate can also be given as the maximum current flowing through a
compensating capacitor. S.R = I/C. Op-amp with slew rate greater than 100V/µs are
termed as “High Speed Op-amps”. For special applications such as video systems,
opamps with slew rate of 1000V/µs are available.
CAUSES OF SLEW RATE:

The worst case, or slowest slew rate, occurs at unity gain. Therefore, slew rate is
usually specified at unity gain. Slew rate depends on many factors: the amplifier gain,
Compensating capacitors, the current flowing through the compensating capacitor and
even whether the output voltage is going positive or negative.
If Vi is a sine wave, with a peak amplitude of Vp, the maximum rate of change of Vi
depends on both its frequency f and peak amplitude. It is given by 2πfVp. If this
change is larger than op-amps slew rate, the output Vo will be distorted.
If a step input is given, it is observed that above certain step amplitude the output slope
saturates at a constant value called slew rate (SR). When the frequency of a train of
square wave given to a voltage follower is constantly increased, the shape of the output
will be a triangular wave instead of square.
Methods of Minimizing Slew Rate
The minimization methods can be summarized with the use of following expression.
SR = 2πIf / gm
81
By increasing the frequency f.
By reducing the input stage transconductance gm.
By increasing the current I flowing through the capacitor.
Or by reducing the value of compensation capacitor Cc (which increases the
frequency)
10. What is the maximum voltage that can be given at the inputs?
Ans: The inputs must be given in such a way that the output should be less than Vsat.
11. Why op-amps cannot be used in open-loop configuration?

Ans: Op-amp in open loop configuration has enormous gain. For example the
op-amp 741 has a typical gain of 200,000 (106 dB) & op-amp OP-77 has a typical gain
of 12 million (141.6 dB). This huge gain is not necessary for most of the application of
op-amp. Since op-amp output will saturate at ±Vsat (positive and negative saturation)
which is approximately equal to ±V (Supply voltage)
12. Can a op-amp be operated using single power supply?

Ans: No. All the general purpose op-amp must be operated with two power
supplies. Since, the differential amplifier has two supply : +Vcc and – Vee, the opamp
which is a multi stage differential amplifier stage must also have two supply voltages.
However, op-amps with single supply voltage are also used for very few applications.
13. Define offset voltage and state its significance.

Ans: When an op-amp has no inputs given, there is a possibility of getting
output because of small voltage at input terminals. This very small voltage difference
between the two terminals of op-amp results due to the slight mismatch between the
characteristics of two transistors present in the starting stage of op-amp. If a small
voltage appears across the input terminals of op-amp, then because of the huge gain of
op-amp, the amplified output will result even when there is no input. So a voltage must
be applied by the user to cancel out the effects. The voltage that must be applied to
nullify the output voltage is called as offset voltage.
14. List the important features of op-amp 741.

Ans: Features of op-amp 741
1. No frequency compensation required.
2. Short circuit protection
3. Offset voltage null capability
4. Large common mode and differential voltage ranges
5. Low power consumption
6. No latch-up
15. Draw the block diagram of op-amp. Ans:
16. How to construct a adder circuit using op-amp?

82
Ans: A two input summing amplifier may be constructed using the inverting
mode. The adder can be obtained by using either non-inverting mode or differential
amplifier. Here the inverting mode is used. So the inputs are applied through resistors
to the inverting terminal and non-inverting terminal is grounded. This is called “virtual
ground”, i.e. the voltage at that terminal is zero. The gain of this summing amplifier is
1, any scale factor can be used for the inputs by selecting proper external resistors.
17. List all Specifications of op-amp 741 Ans:

1. Voltage gain A = α typically 2,00,000
2. I/P resistance RL = α Ω, practically 2MΩ
3. O/P resistance R =0, practically 75Ω
4. Bandwidth = α Hz. It can be operated at any frequency
5. Common mode rejection ratio = α
(Ability of op amp to reject noise voltage)
6. Slew rate + α V/μsec
(Rate of change of O/P voltage)
7. When V1 = V2, VD=0
8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv
9. Input offset current = max 200nA
10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF
12. Offset voltage adjustment range : ± 15mV
13. Input voltage range : ± 13V
14. Supply voltage rejection ratio : 150 μV/V
15. Output voltage swing: + 13V and – 13V for RL > 2KΩ
16. Output short-circuit current: 25mA
17. supply current: 28mA
18. Power consumption: 85mW
19. Transient response: rise time= 0.3 μs
18. Draw the pin configuration of op-amp 741.

Ans:
19. What is the maximum voltage that can be given at the inputs?
Ans: The inputs must be given in such a way that the output should be less than Vsat.
20. How to construct a Subtractor?

Ans: A basic differential amplifier can be used as a subtractor. Input signals can be
scaled to the desired values by selecting appropriate values for the resistors. When this is
done, the circuit is referred to as scaling amplifier. However in this circuit all external
83
resistors are equal in value. So the gain of amplifier is equal to one. The output voltage
Vo is equal to the voltage applied to the non-inverting terminal minus the voltage applied
to the inverting terminal; hence the circuit is called a subtractor.
X- - - - - - X - - - - - - X
EXPT NO: 2
INTEGRATOR AND DIFFERENTIATOR USING OP-AMP.
1. Express the output voltage of an Integrator.
Ans: The expression for the output voltage of an op-amp integrator is given as
1 t
Vo = - Vin dt + C
R1Cf 0
Where R1  Input Resistance
Cf  Feedback Capacitance
Vin  Input Voltage and
C  Constant
2. Why op-amp integrator is called as precision Integrator?

Ans: The op-amp integrator has a high degree of accuracy. And it can precisely
implement the output voltage expression. Because of this, op-amp integrator is often called
as precision integrator.
3. Mention some of the applications of integrator.

Ans: Op-amp integrator finds wide application in function generators (Triangle and
sawtooth wave generators), active filters (State variable & biquad filters, Switched
Capacitor filters), Analog to Digital Converters (Dual-slope converters, Quantized
feedback converters) and Analog controllers (PID Controllers).
4. What are the problems faced by basic ideal integrator and how can we overcome ?
Ans: The input offset voltage Vio and the part of input current charging the
feedback capacitor Cf produces the error voltage at the output of the ideal integrator.
Therefore, in practical integrator, to reduce the error voltage at the output, a resistor Rf is
connected in parallel to Cf. This Rf, limits the low-frequency gain and hence minimizes the
variations in the output voltage. Both stability and the roll-off problems in basic ideal
integrator can be corrected by additional resistor Rf.
5. What is other name given to practical integrator?

Ans: The method of preventing saturation in integrator is to place a parallel
resistance Rf with Cf. The resulting circuit is called as lossy integrator (Practical Integrator)
which can still provide integration function. But, only over a limited frequency range. In
most applications, integrators are placed in a control loop to avoid saturation and there is no
need for Rf in such applications.
6. What is meant by negative resistance?

Ans: Negative resistance indicates the release of power. Negative resistance can be
used to neutralize unwanted ordinary resistance, as in the design of current sources or to
control the pole location, as in the design of active filters and oscillators.
84
7. Integrator is otherwise called as fixed frequency, variable gain LPF. True or
False?
Ans: True.
8. Give the meaning and use of Virtual ground.

Ans: If the difference input voltage is ideally zero, and non-inverting terminal is
grounded with a input signal applied to the non-inverting terminal via R1, then voltage at
the inverting terminal is approximately equal to voltage at the non-inverting terminal. This
is known as virtual ground (A terminal that is not connected to physical ground but,
assumed to be.) It is much used in closed-loop analysis of inverting amplifier.
9. Determine the ouput for the following inputs to an integrator.

1 t
Ans: Since, Vo = - Vindt + C, the output of integrator for the inputs

R1Cf 0
will be Sine Wave  Clamped Cosine Wave
Cosine Wave  Negative Sine Wave
Square Wave  Triangular Wave
Rectangle Wave  Sawtooth Wave
10. How integrator is useful in constructing Servo Amplifer?

Ans: A Servo Amplifier is constructed when an integrator is followed by an inverting
amplifier. Servo amplifiers are used where the output is a delayed response to the input.
Example: Radar (or) Position of a xy table in a manufacturing process.
11. How to convert an op-amp integrator to op-amp differentiator?

Ans: To convert a op-amp integrator to differentiator, just replace the feedback
capacitor Cf as feedback resistor Rf. And replace the input resistor R1 as input capacitor C1
of an integrator.
12. Give the output voltage expression for an integrator.

Ans: The output voltage expression of a differentiator is given as
dVin
Vo = - Rf C1 dt
Where Rf  Feedback Resistance

C1  Input Capacitance
Vin  Input Voltage
13. How ideal differentiator suffers from instability? How can we overcome them?
Ans: The ideal or basic differentiator‟s circuit gain (Rf/R1) increases with increase
in frequency at a rate of +20dB/decade. This makes the circuit unstable. Also, the
impedance Xc1 decreases with increase in frequency, which makes the circuit very
susceptible to high frequency noise. When amplified, this noise can completely override the
differentiated output signal. Both stability and high frequency noise can be corrected by
addition of two components R1 and Cf. This circuit is called as practical differentiator.
14. Can a differentiator be used as a High pass Filter?

85
Ans: Yes, at cut-off frequency of fa = .
15. What is the condition to be followed for proper differentiation?

Ans: The input signal will be differentiated properly if the time period T of the
input signal is larger than equal to RfC1. That is T ≥ RfC1.
16. How high frequency noise affects the performance of an differentiator?

Ans: Due to poor Stability (i.e) Circuit tends to oscillate and gain of the circuit
increases with an increase in frequency. So high frequency noise is amplified and is
dominant at the output.
17. Determine the output of differentiator for the following input waves.
Ans: The inputs and respective output waveform of differentiator are as follows,
Sine Wave  Negative Cosine Wave
Cosine Wave  Sine Wave
Square Wave  Spike Wave
Sawtooth Wave  Square Wave
18. Give some important applications of differentiator.

Ans: Differentiator is most commonly used in wave shaping circuits to detect high
frequency components in an input signal and also as a rate-of-change detector in FM
modulators.
19. What is Unity Gain Frequency?

Ans: Unity-gain frequency of op-amp differentiator is the frequency at which the
gain is unity (0 dB).
20. What is UGB?

Ans: Unity Gain Bandwidth (UGB) is the bandwidth of op-amp when the voltage
gain is 1. It is also called as Closed-loop bandwidth, Gain-Bandwidth Product or Small
signal bandwidth.
X- - - - - X - - - - - X
86
EXPT NO: 3
INSTRUMENTATION AMPLIFIER
1. What are the important requirements of an instrumentation Amplifier?
Ans: The requirements of an instrumentation amplifier are low noise, low thermal
and time drifts, high input impedance, accurate closed-loop gain, high CMRR and high
Slew Rate.
2. List the characteristics of a basic three op-amp instrumentation amplifier.

Ans: For 3 op-amp instrumentation amplifier, the characteristics are
i) The voltage gain, from differential input to single ended output is set by
only one resistor.
ii) The input resistance of both inputs are very high and does not change as
the gain is varied.
iii) Vo does not depend on the voltage common to both inputs (Common-
mode rejection) but, only on their difference.
3. Mention some of the applications of an instrumentation amplifier.

Ans: Instrumentation Amplifier is used in data acquisition unit, sensing,
measurement & Control of physical parameters such as temperature, used as signal
conditioning circuit, Light-intensity meter, Measurement of flow and thermal conductivity,
Analog-weight scale, Active guard drive, digitally programmable gain and output
Offsetting.
4. What are the Different configurations of instrumentation amplifier? What are the
merits and demerits?
Ans: There were four configurations. They are
a. Triple op-amp IAs
b. Dual op-amp IAs
c. Monolithic IAs
d. Flying-Capacitor IAs Triple op-amp IA :
Offers high impedance because of buffer stage and too many components used.
Dual op-amp IA:

Offers less Complexity in circuit (with fewer resistors & op-amps) with
Significant boost in performance. But it treats the input asymmetrically with Some
delay.
Monolithic IA :
Better optimization of CMRR, gain linearity and noise reduction.
Flying-Capacitor IA :
Excellent CMRR, as common mode signals are completely ignored.
5. How many stages does a three op-amp instrumentation amplifier contain?

And what are they?
87
Ans: A common op-amp instrumentation amplifier uses 3 op-amps and seven
resistors which is splitted into two stages. i) Buffer stage (High impedance) Differential
input- differential output stage. ii) Difference amplifier stage.
6. Define CMRR of instrumentation Amplifier.

Ans: CMRR of instrumentation amplifier is defined as ratio of differential mode gain to
common-mode gain.
CMRR (dB) = 20 log │ Ad │

Ac
The Differential mode gain is preferred than common mode gain. Common mode
gain indicates the gain of op-amp when common mode noise signals are present.
7. What is the disadvantage of a instrumentation amplifier?

Ans: The requirement for instrumentation amplifier is too strict to follow for
general purpose applications. When the requirements are not too strict, then a general
purpose op-amp can be used in differential mode. Such amplifiers are called as differential
instrumentation amplifier.
8. Express the individual and overall gain of a instrumentation amplifier. Ans: Gain of
I stage:
Differential output of buffer stage
R3
Vo1 – Vo2 = ( 1 + 2 ) (V1 – V2)
RG
Where V1 - V2  the differential input
R3  feedback resistor of op-amp 1
RGGain varying resistor
Gain of II stage:
Differential output stage
R2
Vo = ( Vo2 – Vo1)
R1
Where Vo2 – Vo1  the differential input to second stage
R2  feedback resistor of op-amp 3
R1 Input resistor of op-amp3 Overall
Gain :
Vo = A(V2 – V1)
R3 R2
Where A = AI x AII = (1+2 )x( )
RG R1
9. Give some examples of a monolithic IAs.
Ans: Examples of IC Instrumentation Amplifiers from Analog Devices
AD 521/522/524/624/625
AMP - 01
AMP – 02
10. What is the use of op-amp buffer?
88
Ans: Op-amp buffer or voltage follower is a unity gain, high input impedance and
very low output impedance circuit used to provide isolation between two stages of an
system.
EXPT NO.4 :
ACTIVE FILTER (LP, HP & BP) USING OP-AMP 741
1. What is meant by passive and active filters?

Ans: Passive filters: Uses Resistors, Capacitors and inductors as elements.
Active Filters: Uses Transistors or op-amps in addition to Resistors and Capacitors.
2. Why active filters are not suitable for high frequency applications?
Ans: Above MHZ range the op-amp open-loop gain rolls-off with increase in
frequency.
3. List some of the applications of filters.

Ans: Filters are an integral part of electronic networks and are used in application
from audio circuits to Digital Signal Processing (DSP) Systems such as speech, audio,
Video, Image processing etc.,
4. How Active filters are superior than passive filters?

Ans: Advantage of active filters over passive filters
i) Gain and frequency adjustment flexibility.
ii) No loading problem.
iii) Low Cost.
5. How Filters are classified and what are they?

Ans: Based on passband, stopband and cutoff frequency, filters are classified into
Lowpass, Highpass, Bandpass, Bandstop and Allpass filters.
6. What are poles and zeros?

Ans: Zeros are numerator and poles are denominator polynomials of the transfer
function of a filter. Poles and Zeros determine the characteristics of a filter.
7. Does a filter affect both amplitude and phase of the input signal? Ans: Yes.
8. What is the use of bode plot?

Ans: The Bode Plots are plots of decibels and degrees versus decades (or Octaves).
The purpose of bode plot is to represent both logarithmic and semi-logarithmic scales.
9. In what basis the order of the filter is decided?

Ans: Based on the parameter „n‟, the order of the filter is decided. n=1; First order,
n=2; Second order and so on. The parameter „n‟ decides the accuracy of the filter primarily
at the stopband (Rolloff). Higher the value of n, better the filter will be and complex the
design will be.
10. Define Bandwidth of a filter.
89
Ans: Bandwidth of a filter is defined as higher cutoff frequency minus lower cutoff
frequency. Or in other words it is the difference between Upper cutoff frequency and
Lower cutoff frequency. Bandwidth is expressed in HZ.
B.W = fH – fL
HZ
11. What do you understand from the frequency response of filter?

Ans: There were three cases that should be noted in any filter except allpass filter.
The three cases for LPF filter for example is given as
Case i: If the input frequency fin is less than the higher cutoff frequency f H, then magnitude
of the gain is maximum and it is given as passband gain of the filter AF. Case ii If the input
frequency fin is equal to the cutoff frequency, then the gain magnitude will be 70.7% of the
A
2
maximum gain. That is, .
Case iii: If the input frequency fin is greater than the higher cutoff frequency fH, then
magnitude of the gain is maximum and it is given as passband gain of the filter AF.
12. What were the different types of BPF? Explain.

Ans: BPF is classified either as Narrowband and Wideband filter based on the
Quality factor (Figure of merit) Q. It is expressed as
fc fc
Q= = ; where fc = fhfl fh fl B.W
If Q < 10 then it is termed as Wide bandpass filter (Poor Selectivity)
If Q > 10 then it is termed as narrow Bandpass filter (Good Selectivity)
13. How filters are classified according to their band characteristics?

Ans: Filters are classified according to their passband and stopband characteristics.
Butterworth  Flat passband and flat stopband (Flat-Flat filter)
Chebyshev  Ripple passbad and flat stopband

Cauer  Ripple passband and Ripple Stopband
14. How to convert a BPF to BSF?

Ans: Swap HPF-LPF series connection of BPF to LPF-HPF series connection to
achieve Bandstop filter (BSF) which is also called as BEF(Band Elimination Filter) or
Notch Filter.
90
15. What is the function of a allpass filter?
Ans: This filter passes all frequencies well but it provides phase shift between input
and Output voltage which is a function of frequency.
16. List the applications of BPF.

Ans: It acts as frequency selector, stereo-equalizer octave filter, communication
transmitter and receiver circuits, radio, TV broadcast receivers, telephone, radar, space
satellites and bio-medical equipment.
17. Write the way of constructing a I order Butterworth BPF.

Ans: I order Butterworth BPF can be constructed using I order Butterworth HPF
followed by I order Butterworth LPF.
18. Why inductors cannot be used with active filters?

Ans: Because, inductors are bulky due to windings and cannot be fabricated inside
an IC.
19. What is the condition for stability of a network?

Ans: All the poles in unit circle must fall on the left half of the S-plane during
mapping for Passive network (Filter) The location of the poles determines the stability
conditions for active network. All the roots must have negative real parts for a active
network (Filter). Also there are no changes in the signs of the first column of the routh
array.
20.
ACL(LPF) = Vo = Af
Vin 1 j( f / fh)
│ ACL │ = Af / √1+ (f/fh)2 ; Ø = tan -1(f/fh)
ACL(HPF) = Vo = Af ( j( f / fl) )
91
Vin 1 j( f / fl)
│ ACL │ = Af (f/fl) / √1+ (f/fl)2 ; Ø = tan -1(f/fl)
Where Af is the passband gain
EXPT NO.5:
ASTABLE, MONOSTABLE MULTIVIBRATOR AND
SCHMITT TRIGGER USING OP-AMP
1. Define multivibrator.
Ans: A multivibrator is an oscillatory circuit capable of generating waveforms
without any Specific input signal. The circuit only has supply voltage connections, from
which the two amplifiers saturates one another to generate vibrations.
2. State the relationship between Astable multivibrator and a comparator.

Ans: Astable multivibrator is almost a comparator except the trigger or threshold
voltage will be generated on its own.
3. Express the frequency of oscillation of an Astable Multivibrator. Ans: The

frequency of oscillation of free running multivibrator is given as
1 1
fo = =
T 2 RC ln(1 2 R1 / R 2)
4. What is the major difference between astable and monostable multivibrator? Ans:
In astable multivibrator there is no stable state and no triggering input. But,
monostable multivibrator has one stable state and works based on the triggering pulse
input.
5. Which Determines the switching time of a multivibrator?

Ans: The threshold value determines the switching time of a multivibrator. When
ever a capacitor voltage exceeds │VT│, the output state changes.
6. List some applications of multivibrator.

Ans: Multivibrators are mostly used for timing applications. Astable multivibrator
is primarily used as square wave generator in a function generator.
Monostable
Multivibrator is used for timed control applications with the help of triggering input.
7. Say how to form a triangular wave generator using multivibrator?

Ans: To construct a triangular wave generator, a Astable multivibrator should be
followed by an integrator. Square wave is generated first and then converted to triangular
with the help of integrator.
8. Define stable state.

92
Ans: The time over which a multivibrator output voltage stays constantly is called
as stable state. A quasi-stable in the other hand depends on the triggering input to regain the
output state.
9. Give the expression of period of oscillation of an Astable multivibrator. Ans: The

expression for period of oscillation of a free running multivibrator is
given as T = 2RC ln (
2
R1 R2
)
R2
10. Give the relationship between tp and T of a monostable multivibrator.

Ans: The Triggering pulse width „tp‟ must be much smaller than the ON time
„T‟ of Stable State.
11. What is a Schmitt trigger?

Ans: Schmitt trigger is the inverting comparator with positive feedback. The other
names given for Schmitt trigger circuit is regenerative comparator and squaring circuit. It is
mainly used in converting any irregular shaped waveform into square wave or pulse. So it
is used in wave shaping circuit.
12. Give the expression for the upper and lower threshold points of Schmitt trigger.
Ans: The expression for upper threshold point and lower threshold point are as
follows
R1
Upper threshold voltage VUT = (+Vsat)
R1 R2
Lower
threshold voltage VLT =
R1
(-Vsat)
R1 R2
13. Write the truth table of a comparator.
Ans: Truth table of a Comparator When V+
> V-  +Vsat When V+ < V-  -
Vsat
When V+ = V-  High Impedance State
14. What is Comparator chatter? And how can we eliminate it?

Ans: For slowly varying signals, comparators tend to produce multiple output
transitions, or bounces, as input crosses the threshold region. This is referred to as
comparator chatter. This phenomenon is eliminated with the help of Hysteresis. In
hysteresis the circuit snaps and activates the other threshold.
15. What happens when both threshold points in a Schmitt trigger is equal to zero?
Ans: When VUT = VLT = 0, the Schmitt trigger behaves as a zero crossing
detector. There were two types of Schmitt trigger. They are positive and negative
Schmitt trigger.
93
16. Can a Schmitt trigger can be operated with single supply & single threshold
voltage?
Ans: Schmitt trigger can also be operated with single power supply or with a single
triggering input (Either Positive or Negative)
X - - - - - - X - - - - -X
EXPT NO.6:
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR
USING OP-AMP 741
1. State Barkhausen Criterion and its significance.
Ans: Barkhausen Criterion for oscillation gives the conditions for an oscillator to
oscillate.
i) AVβ ≤ 1; the product of forward gain AV and the feedback ratio β must
satisfy this condition.
ii) The total phase shift of AVβ must be 0° or 360°
2. According to oscillations how oscillators are classified?

Ans: Based on how oscillations are created, oscillations are classified as under
damping, over damping and constant amplitude oscillations.
3. How oscillations are created in RC phase shift and wien Bridge oscillator?
Ans: When the bridge is balanced and the overall phase attained is 0°, the Wien
bridge oscillator produces oscillations. RC phase shift oscillator produces 360° of phase
shift in two parts. Firstly, each and every RC pair in the feedback network produces 60°
phase shift and a totally there were three pairs, thus producing 180° Phase shift and
secondly, the feedback input is given to the inverting terminal of opamp to produce
another 180° phase shift and a total phase shift of 360°.
4. What are the merits and demerits of different types of oscillator?

Ans: The major problem in Wien bridge oscillator is balancing the bridge
becomes very difficult when the component values drifts unfortunately due to external
94
or internal conditions. Poor stability and low frequency application is the demerits of
RC phase shift Oscillator. Both RC phase shift and Wien bridge oscillator have a
advantage that its operating frequency can be easily varied by just replacing the values
of either R or C to a new value. Crystal oscillator has excellent stability and poor
deviation.
5. Give the expression for frequency of oscillation of RC phase shift oscillator and
Wien bridge oscillator.
Ans: The frequency of oscillation of RC phase shift oscillator is given as

fo = 1/(2π√6 RC)
1
2 RC
The frequency of oscillation of a Wien bridge oscillator is given as fo =
EXPT NO.7:
ASTABLE AND MONOSTABLE MODE OF IC 555 TIMER
1. Why Timer IC is numbered as 555?

Ans: The timer IC is called as 555, because the internal architecture consists of
three 5KΩ resistors.
2. What are the different operating modes of 555 Timer?

Ans: There were two operating modes of 555 Timer. It operates in Astable and
Monostable mode.
3. What are the different types of packages available for 555 Timer IC?
Ans: The packages used for 555 Timer are 8-pin mini Dual-Inline-Package (DIP)
and 8-pin Metal Can.
4. List some applications of 555 timers in both Astable mode and Monostable
Mode.
Ans: In Astable mode of operation, some of the applications of 555 Timer were:
Tone- burst oscillator, Voltage controlled frequency shifter, square wave generator etc., In
Monostable or one-shot mode, some of the applications of 555 timer were: Water-level fill
control, Touch switch, Frequency divider, missing pulse detector and many more.
5. Define duty cycle.

Ans: Duty cycle of waveform if defined as the ration of ON time of the wave
95
Ton
to the total time. τ = Ttotal
Example: If a square wave is On for 1ms of time and if the total time is 2ms,
The duty cycle is 0.5 or in terms of percentage = 50%.
6. Express the free running frequency of oscillation and total period of Astable mode
of 555 timer.
Ans: The free running frequency of oscillation is given as
1 1.44
f= = and thus the total period of oscillation T is
T (Ra 2Rb)C
T = 0.695
(Ra+2Rb)C
X - - - - - - X - - - - -X
EXPT. NO: 8
PLL IC 565 AND FREQUENCY MULTIPLIER USING PLL 565
1. What is a PLL?
A PLL is a Phase Locked Loop Circuit used to track any changes in the input
frequency.
2. What are the operating modes of an PLL?

A PLL functions in any in any one of the mode described here.
1) Free Running mode
2) Capture mode
3) Lock mode and
4) Tracking mode/range
3. What are the basic building blocks of a PLL IC?

The basic building blocks of PLL IC are 1) Phase comparator 2) Low Pass
Filter and 3) Error Amplifier.
4. What is meant by free running mode of a PLL?

A PLL is said to be in this mode when there is no input frequency given to
phase comparator for comparison. When no input is given, PLL runs freely without
any locking or tracking and so it is called as free running mode of PLL.
5. Name some of the applications of PLL IC 565.

PLL ICs are mostly used in frequency application circuits such as Frequency
synthesizer, frequency multiplier, frequency divider, phase comparator, FM
demodulator, PM demodulator, Phase magnitude comparator, etc.,
6. Why PLL Circuit is mostly preferred in Frequency Applications?
96
It is preferred in most of the frequency applications because the frequency
content of a signal is indirectly proportional to Phase of the same signal. As we
compare the phase of the two signals, we indirectly compare the frequency of the
same signal. This is due to the fact that direct phase is nothing but indirect
frequency and direct frequency is nothing but indirect phase.
7. What happens when the two input signals given to PLL is having same
frequency or same phase?
When both the inputs are same, the PLL will start functioning in the Lock
mode and if once lock has been occurred, the PLL will start tracking the Phase or
frequency changes in the input signal.
8. What is VCO?
VCO is the integral part of PLL. A VCO is the Voltage Controlled
Oscillator. As the name implies it generates oscillations according to the input
voltage. This VCO is placed in the feedback path of a PLL. The output of the VCO
is changing according to the Error output voltage from the error amplifier placed
finally in the forward path.
X - - - - - - X - - - - -X
ADDITIONAL SYLLABUS VIVA-VOCE Q & A
EXPT NO.12
DIGITAL TO ANALOG CONVERTER USING OP-AMP 741
1. Mention Some Important DAC characteristics.
Ans: Resolution, Full-scale output Voltage, Offset error, Gain error, Monotonocity
and Relative accuracy.
2.What are the different types of D/A Converter techniques available? Ans:
The different types of DAC techniques are i) Binary weighted
DAC ii) R-2R Ladder network iii) Inverted R-2R ladder
network
iv) Current Driven DAC
3. Define resolution of a DAC.

Ans: The resolution is nothing but the number of distinct analog outputs that can be
produced by DAC. It is given as Resolution = 2n Where „n‟ is the number of digital inputs.
Example: For 3 inputs DAC there are 8 distinct outputs.
4. What were the practical resolutions possible?

Ans: DACs with resolution of 8, 10, 12, 14, 16, 18 and 20 bits were already
available.
5. Define monotonicty of a DAC.

Ans: A DAC is said to be monotonic if the analog output increases or remains the
same as the digital input increases. This result in the output always single valued.
97
6. What are the merits and demerits of different types of DAC conversion techniques?
Ans: The binary weighted is the simplest DAC technique. But this technique suffers
from the fact that if, number of binary inputs was more, then the Value of resistor also
increases and becomes difficult to be implemented inside a IC.
The R-2R ladder network eliminates the above said disadvantage, since it uses only
two values of resistance R and 2R irrespective of number of binary inputs. Ratioed emitter
current is the disadvantage of this type.
The inverted ladder type eliminates the above said disadvantage by performing
voltage ratio rather than current ratio.
Current driven DAC is mainly used when there is a base errors. This type is mainly used to
compensate base losses of a bipolar DACs.
7. Mention some monolithic DACs available.

Ans: DAC – 08, AD 558, PCM 52/53 nad HI-DAC 16 are some of the examples of
monolithic DAC.
X - - - - - - X - - - - -X
98

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BHARATHIDASAN ENGINEERING COLLEGE.

M.G.R Nagar, K.Bandarapalli, Nattarampalli – 635 854.

DEPARTMENT OF ELECTONICS AND COMMUNICATION ENGINEERING

EC8462 – LINEAR INTEGRATED CIRCUITS LAB.

Register Number : _________________________

Degree / Branch : B.E. / Electronics and Communication Engineering

Year / Semester : 2nd Year / 4th Semester

DESIGN AND TESTING OF

1. Inverting, Non inverting and differential amplifiers.

SIMULATION USING SPICE

1. Active low-pass, High-pass and band-pass filters using Op-amp

Theoretical Gain Practical Gain

S.NO COMPONENTS RANGE QUANTITY

V in Theoretical Gain Practical Gain

PROCEDURE-(INVERTING & NON-INVERTING AMPLIFIER):-

6. Practical gain & theoretical gain should be approximately equal.

S. V in1 Vin2 Vin2 - Vin1 V0 Theoretical Gain Practical Gain

A configuration which combines inverting & non-

4. Measure the output voltage using CRO.

S.NO COMPONENTS RANGE QUANTITY

Integrator as LPF (Characteristics of integrator)

Design of integrator with a lower frequency (Break Frequency) limit of integration

2. Input Voltage (Vin peak)

3. Input Time Period (tVin)

4. Output Voltage (Vout peak)

5. Output Time Period (tVo)

MODEL GRAPH: SINE WAVE INPUT

(ii) SQUARE WAVE INPUT

Design of integrator to integrate at cut-off frequency 1 KHz.

Always take Cf < μf and

SINE WAVE INPUT:

COMMON MODE GAIN CALCULATION AC

S.NO COMPONENTS RANGE QUANTITY

An instrumentation amplifier is the intermediate stage of a instrumentation system.

The major requirements of a instrumentation amplifier are precise, low-level signal

2. Connect the circuit as shown in the circuit diagram.

CMRR as CMRR=20 log . Ad

S.NO COMPONENTS RANGE QUANTITY

THEORY – (ACTIVE LPF):-

1. Gain & frequency adjustment flexibility.

off. The frequency range from 0 to fH is called as Passband & fH to is called as

Stopband. Out of Butterworth, chebyshev & cauer filters, Butterworth filter is

LOWPASS FILTER:- CIRCUIT DIAGRAM:-

Frequency Output Voltage Gain = 20 log (V 0

DESIGN PROCEDURE: (ACTIVE HPF):

PROCEDURE - (LPF & HPF):

3. Connect the circuit as shown in the circuit diagram.

5. Tabulate the output voltage Vo with respect to different values of input

6. Calculate the values of Rf & R1 with the use of

Where fC = fH fL is the center frequency.

2. Select the value of C < 1μf

5. Calculate the practical gain in dB using Gain (dB)=20log (Vo/Vin);

DESIGN OBSERVED VALUE

S.NO COMPONENTS RANGE QUANTITY

operate in the saturation region (±Vsat). A fraction β = of the output is

2. To simplify the above expression, the value of R1 & R2 should be taken as R2

3. Assume the value of R1 = 10KΩ and find R2. R2 = 1.16KΩ (10K)

5. Calculate the threshold point from

Amplitude Time period