EC8462

DMI COLLEGE OF ENGINEERING

PALANCHUR CHENNAI – 600 123

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
LABORATORY MANUAL
SUB CODE : EC8462

SUBJECT TITLE: LINEAR INTEGRATED CIRCUITS LABORATORY
SEMESTER : IV
YEAR : II
DEPARTMENT : ELECTRONICS AND COMMUNICATION ENGINEERING
EC8462-Linear Integrated Circuits Laboratory Dept of Electronics & Communication Engg
Vision of the Department
To develop committed and competent technologists in electronics and communication

engineering to be on par with global standards coupled with cultivating the innovations and
ethical values.
Mission of the Department:
DM 1: To be a centre of excellence in teaching learning process promoting active learning with
critical thinking.
DM 2: To strengthen the student’s core domain and to sustain collaborative industry interaction
with internship and incorporating entrepreneur skills.
DM 3: To prepare the students for higher education and research oriented activities imbibed with
ethical values for addressing the social need.
PROGRAM EDUCATIONAL OBJECTIVES (PEOs):
PEO1. CORE COMPETENCY WITH EMPLOYABILITY SKILLS: Building on

fundamental knowledge, to analyze, design and implement electronic circuits and
systems in Electronics and Communication Engineering by applying knowledge of
mathematics and science or in closely related fields with employability skills.
PEO2. PROMOTE HIGHER EDUCATION AND RESEARCH AND
DEVELOPMENT: To develop the ability to demonstrate technical competence and
innovation that initiates interest for higher studies and research.
PEO3. INCULCATING ENTREPRENEUR SKILLS: To motivate the students to
become Entrepreneurs in multidisciplinary domain by adapting to the latest trends in
technology catering the social needs.
PEO4. ETHICAL PROFESSIONALISM: To develop the graduates to attain
professional excellence with ethical attitude, communication skills, team work and
develop solutions to the problems and exercise their capabilities.
1
DMI College of Engineering
PROGRAM OUTCOMES (POs)
The Program Outcomes (POs) are described as.
1. Engineering Knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals and an engineering specialization to the solution of complex
engineering problems.
2. Problem Analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first principles
of mathematics, natural sciences, and engineering sciences.
3. Design / Development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge
to assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual and as a member
or leader in diverse teams, and in multidisciplinary settings.
2
10. Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large, such as, being able to comprehend
and write effective reports and design documentation, make effective presentations, and
give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of
the engineering management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for and have the preparation and ability to
engage in independent and lifelong learning in the broadest context of technological
change.
PROGRAM SPECIFIC OUTCOMES (PSOs):
PSO1. Analyze and design the analog and digital circuits or systems for a given
specification and function.
PSO2. Implement functional blocks of hardware-software co-designs for signal

processing and communication applications.
PSO3. Design, develop and test electronic and embedded systems for applications with
real time constraint and to develop managerial skills with ethical behavior to work in a
sustainable environment.
3
INSTRUCTIONS TO STUDENTS FOR WRITING THE RECORD
In the record, the index page should be filled properly by writing the corresponding
experiment number, experiment name , date on which it was done and the page number.
On the right side page of the record following has to be written:
1. Title: The title of the experiment should be written in the page in capital letters.
2. In the left top margin, experiment number and date should be written.
3. Aim: The purpose of the experiment should be written clearly.
4. Apparatus/Tools/Equipments/Components used: A list of the Apparatus/Tools/
Equipments/ Components used for doing the experiment should be entered.
5. Theory: Simple working of the circuit/experimental set up/algorithm should be written.
6. Procedure: Steps for doing the experiment and recording the readings should be briefly
described(flow chart/ Circuit Diagrams / programs in the case of computer/processor
related experiments)
7. Results: The results of the experiment must be summarized in writing and should be
fulfilling the aim.
On the Left side page of the record following has to be recorded:
1. Circuit/Program: Neatly drawn circuit diagrams for the experimental set up.
2. Design: The design of the circuit components for the experimental set up
for selecting the components should be clearly shown if necessary.
3. Observations:
i) Data should be clearly recorded using Tabular Columns.
ii) Unit of the observed data should be clearly mentioned
iii) Relevant calculations should be shown. If repetitive calculations are needed, only show a
sample calculation and summarize the others in a table.
4
EC8462 LINEAR INTEGRATED CIRCUITS LABORATORY LT PC

0 0 4 2
LIST OF EXPERIMENTS:
DESIGN AND TESTING OF THE FOLLOWING CIRCUITS
1. Inverting, Non inverting and Differential amplifiers.
2. Integrator and Differentiator.
3. Instrumentation amplifier
4. Active low-pass, High-pass and band-pass filters.
5. Astable & Monostable multivibrators using op-amp.
6. Schmitt Trigger using op-amp.
7. Phase shift and Wien bridge oscillators using op-amp.
8. Astable and monostable multivibrators using NE555 Timer.
9. PLL characteristics and its use as Frequency Multiplier, Clock synchronization
10. R-2R Ladder Type D- A Converter using Op-amp.
11. DC power supply using LM317 and LM723.
10. Study of SMPS.
SIMULATION USING SPICE

1. Active low-pass, High-pass and band-pass filters using Op-amp
2. Astable and Monostable multivibrators using NE555 Timer.
3. A/ D converter
4 . Analog multiplier
TOTAL: 60 PERIODS
5
Course outcomes:
CO 1 Design oscillators and amplifiers using operational amplifiers
CO 2 Design filters using Opamp and perform experiment on frequency response
CO 3 Analyse the working of PLL and use PLL as frequency multiplier
CO 4 Design DC power supply using ICs.
CO 5 Analyse the performance of oscillators and multivibrators using SPICE
CO , PO, PSO Mappings
Course
Program Outcomes PSO
Code and
CO
Course
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
name
CO 1 3 2 2 2 3 2 - - 3 3 - 2 3 3 3
EC8462 CO 2 3 2 2 3 3 2 - - 3 2 - 2 3 3 3
Linear
Integrated CO 3 3 2 3 2 3 3 - - 3 3 - 2 3 3 3
circuits
Laboratory CO 4 3 3 2 2 3 3 - - 3 2 - 2 3 3 3
CO 5 3 2 2 3 3 3 - - 2 3 - 2 3 3 3
Average 3 2.2 2 2.4 3 3 - - 3 3 - 2 3 3 3
6
INDEX
EX.No. LIST OF THE EXPERIMENT PAGE NO
INVERTING, NON-INVERTING AND DIFFERENTIAL

1 11
AMPLIFIERS USING OP-AMP
2 INTEGRATOR AND DIFFERENTIATOR USING OP-AMP 16
3 INSTRUMENTATION AMPLIFIER 22
ACTIVE LOW PASS, HIGH PASS AND BAND PASS FILTER

4 25
USING OP-AMP
ASTABLE, MONOSTABLE MULTIVIBRATOR AND

5 32
SCHMITT TRIGGER USING OP-AMP
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR

6 40
USING OP-AMP
ASTABLE & MONOSTABLE MULTIVIBRATOR

7 46
USING IC 555 TIMER
PLL CHARACTERISTICS AND FREQUENCY

8 54
MULTIPLIER USING PLL
9 R-2R LADDER TYPE D- A CONVERTER USING OP-AMP. 57
10 DC POWER SUPPLY USING LM317 AND LM723 60
STUDY OF SMPS
11 65
7
EX.No. LIST OF THE EXPERIMENT PAGE NO
SIMULATION OF ACTIVE LOWPASS, HIGH PASS AND

12 69
BAND PASS FILTER USING PSPICE
SIMULATION OF ASTABLE AND MONOSTABLE

13 72
MULTIVIBRATORS USING NE555 TIMER
SIMULATION OF ADC,DAC AND ANALOG

14 76
MULTIPLIER USING PSPICE
CONTENT BEYOND THE SYLLABUS
15 CHARACTERISTICS OF OP-AMP 79
16 APPLICATIONS OF OP-AMP 83
8
IC 741 - General Description:

The IC 741 is a high performance monolithic operational amplifier constructed
using the planar epitaxial process. High common mode voltage range and absence of latch-up
tendencies make the IC 741 ideal for use as voltage follower. The high gain and wide range of
operating voltage provides superior performance in integrator, summing amplifier and general
feed back applications.
Pin Configuration:
Block Diagram of Op-Amp:
Features:
1. No frequency compensation required.
2. Short circuit protection
3. Offset voltage null capability
4. Large common mode and differential voltage ranges
5. Low power consumption
6. No latch-up
9
SPECIFICATIONS:-
1. Voltage gain A =  typically 2,00,000
2. Input resistance RL =  Ω, practically 2MΩ
3. Output resistance R =0, practically 75Ω
4. Bandwidth =  Hz. It can be operated at any frequency
5. Common mode rejection ratio = 
(Ability of op amp to reject noise voltage)
6. Slew rate +  V/μsec
(Rate of change of O/P voltage with respect to applied I/P)
7. When V1 = V2, VD=0
8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv
9. Input offset current = max 200nA
10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF
12. Offset voltage adjustment range : ± 15mV
13. Input voltage range : ± 13V
14. Supply voltage rejection ratio : 150 μV/V
15. Output voltage swing: + 13V and – 13V for RL > 2KΩ
16. Output short-circuit current: 25mA
17. supply current: 28mA
18. Power consumption: 85mW
19. Transient response: rise time= 0.3 μs
Overshoot= 5%
APPLICATIONS:-
1. AC and DC amplifiers.
2. Active filters.
3. Oscillators.
4. Comparators.
5. Regulators., etc.,
10
INVERTING, NON-INVERTING AND DIFFERENTIAL

EXP.NO: 01
AMPLIFIERS USING OP-AMP
AIM:
To design the Inverting, Non-Inverting and Differential Amplifiers using
Op-amp IC741 and test their performance.
APPARATUS REQUIRED:
S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 01
1KΩ, 33KΩ EACH 01
2. RESISTORS
10KΩ, 100 KΩ. EACH 02
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW
NON-INVERTING AMPLIFER:-
CIRCUIT DIAGRAM:-
Rf=1K,10K,33K,100K.
+15v
R1=10K 2 - 7
IC 741
+ 6
+ 3 4 +
Signal V~
in CRO
Generator -15v
- -
TABULATION:
Input Output
Amplitude
Time Period
11
MODEL GRAPH:
Vin
INPUT
Time (ms)
OUTPUT
Vout
Time (ms)
INVERTING AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf=1K,10K,33K,100K.
+15v
R1=10K 2 7
-
IC 741
Signal + 6
Generator + 3 4 +
~
Vin CRO
-15v
- -
TABULATION:
Input Output
Amplitude
Time Period
12
MODEL GRAPH:
Vin
INPUT
Time (ms)
Vout
OUTPUT
Time (ms)
PROCEDURE-(INVERTING & NON-INVERTING AMPLIFIER):-

1. Select R1 as a constant value and choose a value of Rf.
2. Connect the circuit as per as the circuit diagram.
3. Apply the constant amplitude input voltage to the circuit.
4. Measure the output voltage amplitude for different value of R f from CRO.
5. Calculate the practical gain for different value of R f & compare it with theoretical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.
13
DIFFERENTIAL AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf=R2=100K
+15v
R1=10k 2 - 7
IC 741
+ + 6
+ R1=10K 3 4 +
R2=100K V
Vin 1 Vin 2 VO
-15v
- -
-
TABULATION:
Vin1 Vin2 Vin2 - Vin1 V0 Theoretical Gain Practical Gain

S.No
(Volts) (Volts) (Volts) (Volts) A = -Rf / R1 A=V0 / (Vin2 - Vin1)
14
PROCEDURE:
1. Select the value of R1, R2, R3 & Rf such that R1=R2 and R3=Rf.
3. Provide constant input voltage Vin1 to Non-inverting terminal of op-amp through R1 &
constant input voltage Vin2 to inverting terminal of op-amp through R2.
4. Measure the output voltage using CRO.
5. Calculate the theoretical gain and compare it with practical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.
RESULT:
Thus the Inverting, Non-Inverting and Differential Amplifiers are designed and
their performance was successfully tested using op-amp IC 741.
15
EXP.NO: 02 INTEGRATOR AND DIFFERENTIATOR USING OP-AMP
AIM:
To design an Integrator and Differentiator using op-amp IC 741 and to test their
characteristics & Performance.
APPARATUS REQUIRED:

1. IC 741 --- 01
100 Ω, 1.5KΩ Each 02
2. RESISTORS
10KΩ, 15KΩ Each 01
0.1μf, 0.01μf Each 01
3. CAPACITOR
0.001μf, 05
PROCEDURE:
1. From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are calculated as given
in the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the sinusoidal input as the constant amplitude to the inverting terminal of op-amp.
4. Gradually increase the frequency & observe the output amplitude.
5. Calculate the gain with respect to frequency & plot its graph.
16
INTEGRATOR:-
CIRCUIT DIAGRAM:-
TABULATION:
Input Output
Amplitude
Time Period
MODELGRAPH:
17
DIFFERENTIATOR:-
CIRCUIT DIAGRAM:
TABULATION:
Input Output
Amplitude
Time period
MODEL GRAPH:
(i) FOR SINE WAVE INPUT
18
PROCEDURE:
1. Select fa equal to the highest frequency of the input signal to be differentiated. Calculate
the component values of C1 & Rf.
2. Choose fb = 20fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of op-amp through R1
C1.
5. Observe the shape of the output signal for the given input in CRO.
6. Note down the reading and plot the graph of input versus output wave for both cases.
(ii) FOR SQUARE WAVE INPUT
19
DESIGN PROCEDURE-(INTEGRATOR):-
Design of integrator to integrate at cut-off frequency 1 KHz.
1
Take fa =
2R f C f
= 1 KHz.
Always take Cf < 1 μf and
Let Cf = 0.01μf
1
Rf =
2C f f a
Rf = 15.9KΩ
Rf = 15 KΩ
1
Take fb = = 10 KHz.
2R1C f
1
R1 = = 1.59 KΩ.
2f b C f
R1 ≈ 1.5KΩ
R1 R f
Rcomp = R1 // Rf = ≈ R1, Assume RL = 10KΩ
R1  R f
Rcomp = 1.5KΩ
DESIGN PROCEDURE-(DIFFERENTIATOR):-
Design a differentiator to differentiate an input signal that varies in frequency from 10Hz
to 1KHz. Apply a sine wave & square wave of 2Vp-p & 1 KHz frequency & observe the output.
To find Rf & C1
Given: fa = 1 KHz.
1
fa =
2R f C1
fa = 1KHz.
Assume C1 = 0.1μf
Rf = 1.59KΩ ≈ 1.5KΩ
20
To find R1 & Cf
Select fb = 20fa with R1C1 = Rf Cf
1
fb = 20KHz =
2R1C1
R1 = 79.5Ω ≈ 100Ω
R1C1 82 X 0.1X 10 6
Cf = =
Rf 1.5K
Cf = 0.005μf.
ROM ≈ R1 // Rf = 100Ω
SINE WAVE INPUT:

Vp-p = 2V f=1KHz
Vp = 1V,
Vin = Vp sin  t
= sin (2  )(103)t
dVin
Vo = - RfC1
dt
d
= -(1.5KΩ) (0.1μf) [sin [(2  )(103)t]
dt
= -(1.5KΩ) (0.1μf) (2  ) (103) cos [(2  )(103)t]
= - 0.94 cos [(2  )(103)t]
RESULT:
Thus an Integrator and Differentiator using op-amp are designed and their performance
was successfully tested using op-amp IC 741.
21
EXP.NO: 03 INSTRUMENTATION AMPLIFIER
AIM:
To construct and test the CMRR (Common Mode Rejection Ratio) of a 3 op-amp
instrumentation amplifier using op-amp IC741.
APPARATUS REQUIRED:

1. IC 741 03
1KΩ. 06
2. RESISTORS
22KΩ 01
PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let RG be the gain varying
resistor with different values of resistance. For simplicity, let RG be a constant value.
3. Give the input V1 & V2 to the non-inverting terminals of first & second
Op-amp respectively.
4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide different input
value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to calculate the
Ad
CMRR as CMRR=20 log .
Ac
22
CIRCUIT DIAGRAM:
+15v
3 7
+IC 741
Rf=1K
6
2 - 4
+15v
R2=1K
-15v
R1=1K 2 7
-
IC 741
6
RG=22K 3 + 4
+ R1=1K
V1 -15v
R2=1K
- +
+15v R1=1K V
-
2 7
-
IC 741
6
+ 3 + 4
V2
-15v
-
TABULATION:
COMMON MODE GAIN CALCULATION - AC
Vo
RG V1 V2 Vo Ac =
S.No V1  V2
(KΩ) (Volts) (Volts) (Volts)
2
1.
2.
3.
4.
5.
23
DIFFERENTIAL MODE GAIN - AD & CMRR CALCULATION.
Vo CMRR =
V1 V2 Vo
S.No RG (KΩ) Ad = A
20 log ( d
(Volts) (Volts) (Volts) V1  V2 Ac
)(dB)
1.
2.
3.
4.
5.
RESULT:
Thus a 3 op-amp instrumentation amplifier was constructed and CMRR is tested
using op-amp IC 741.
24
EXP.NO: 04 ACTIVE LOW PASS, HIGH PASS AND BAND PASS

FILTER USING OP-AMP
AIM:
To design an Active Low Pass, High Pass and Band Pass Filter using op-amp and to test
their performance
APPARATUS REQUIRED:

1. IC 741 --- 02
1.5 KΩ 02
2. RESISTORS 10KΩ 01
22KΩ 04
3. CAPACITORS 0.1μf, 0.01μf 01
DESIGN PROCEDURE: (ACTIVE HPF):
Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same procedure
as LPF & interchange the R & C position with capacitor first & resistor in parallel to capacitor
where the other end connected to ground.
Vo Af ( f / f L )
In high pass filter Theoretical gain is given as =
Vin 1  ( f / f H )2
PROCEDURE - (LPF & HPF):

2. Select the corresponding cut-off frequency (higher or lower) and determine the value of
C & R. select the value of R1 & Rf depending on desired passband gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of op-amp.
4. Tabulate the output voltage Vo with respect to different values of input frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain & check the
graph to get approximately the same characteristic as shown in the model graph.
25
LOWPASS FILTER:-
CIRCUIT DIAGRAM:-
R1=22K Rf=22K
+15v
2 - 7
Signal IC 741
Generator 1.5K 6
3 + 4
+ +
RL=10K
Vin ~ 0.1uf
-15v
CRO
-
TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODEL GRAPH:
26
CIRCUIT DIAGRAM - (HIGH PASS FILTER):-

R1=22K Rf=22K
+15v
2 7
-
Signal 0.1μf IC 741
Generator 6
3 + 4 +
+
RL=10K
Vin ~ 1.5K -15v
CRO
-
TABULATION:
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODEL GRAPH:
27
CIRCUIT DIAGRAM: (BANDPASS FILTER)

R1=22K Rf=22K
R1=22K Rf=22K
+15v
+15v
2 7
2 7
-
Signal C=0.1uf
- IC 741
6
Generator IC 741 3 + 4
6 R=1.5K
3 + 4 +
+ -15v CRO
Vin ~ R=1.5K
-15v
C=0.01uf
RL=10K -
-
First Order High Pass Filter First Order Low Pass Filter
TABULATION:

S.No
(Hz) (Volts) (dB)
1
2
3
4
5
6
7
8
MODEL GRAPH:
28
PROCEDURE:
1. Select the lower and higher cut-off frequency and calculate the value of R & C for the
given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing the HPF
followed by a LPF (i.e.) HPF in series with LPF.
4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of op-amp.
5. Tabulate the output voltage Vo with respect to different values of input frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain & check the
graph to get approximately the same characteristic as shown in the model graph.
DESIGN PROCEDURE - (ACTIVE BPF):-
Design a BPF to pass a band of 1 KHz to 10 KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as fH = 10 KHz and the lowest cut-off
frequency of HPF as fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
fL = ; Therefore R1 =
2RC 2f L C
1
R= ;
2 (1KHz )(0.1X 10 6 )
R = 1.59KΩ ≈ R=1.5KΩ
4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1μf. Let C =
0.01μf.
1 1
5. Calculate R from the expression fH = ; Therefore R =
2RC 2f H C
1
R= ;
2 (10 KHz )(0.01X 10 6 )
R = 1.59KΩ ≈ R=1.5KΩ
6. Calculate the values of Rf & R1 with the use of pass band gain.
Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF)
29
Therefore for both HPF & LPF the value of R f = R1 to obtain a individual P.B gain of 2.
Rf
Af = (1+ ) = 2 (for HPF)
R1
Rf
Af = (1+ ) = 2 (for LPF)
R1
Let Rf = R1 = 22KΩ.
fc fc
7. Q of the filters is calculated as =
B.W fH  fL
Where fC = f H f L is the center frequency.

8. Cascade HPF & then LPF to form BPF.
Calculate the practical gain dB using 20 log (Vo/Vin)
f
Vo Af T ( )
And Theoretical gain is = fL
Vin f 2 f 2
[1  ( ) ][1  ( ) ]
fH fL
DESIGN PROCEDURE (ACTIVE LPF):

Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.
1. Choose the given value of fH = 1KHz.
2. Select the value of C < 1μf

1
3. Assume C = 0.1μf. Calculate R from fH =
2RC
1
R=
2f H C
1
R= = 1.5KΩ
2X 1X 10 3 X 0.1f
R = 1.5KΩ C = 0.1μf
4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + = 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ & Assume RL = 10KΩ
30
5. Calculate the practical gain in dB using Gain (dB)=20log (Vo/Vin);

Vo Af
Theoretical gain is given as =
Vin 1  ( f / f H )2
Af – P.B gain.
f – Input frequency.
fH – Higher cut-off frequency of LPF.
RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed and tested using
op-amp IC 741.
31
EXP.NO: 05 ASTABLE , MONOSTABLE MULTIVIBRATOR AND SCHMITT

TRIGGER USING OP-AMP
AIM:
To design an Astable, Monostable multivibrator and Schmitt trigger using op-amp
IC 741 and to test their characteristics.
APPARATUS REQUIRED:

1. IC 741 --- 01
100Ω, 100KΩ,
EACH 01
2. RESISTORS 22 KΩ
10KΩ, 47KΩ, EACH 03
3. CAPACITORS 0.01μf, 0.1μf 01
4. DIODE 1N4007 02
DESIGN PROCEDURE:-
Design of square wave generator at f0 = 1 KHz.
1. The expression of fo is obtained from the charging period t 1 & t2 of capacitor as
1
fo =
2 RC ln[ 1  (2 R1 / R2 )]
2. To simplify the above expression, the value of R1 & R2 should be taken as
1
R2 = 1.16R1, such that fo simplifies to fo =
2 RC
3. Assume the value of R1 = 10KΩ and find R2. R2 = 1.16KΩ (10K)

R2 = 11.6KΩ (DRB)
Adjust the value of R2 till 22 KΩ for getting better output.
32
1
4. Assume the value of C & Determine R from fo =
2 RC
Let C = 0.01μf
1 1
R= =
2 f oC 2 X (1X 10 )(0.01X 10 6 )
3
R = 50KΩ ≈ 47KΩ
5. Calculate the threshold point from

R1
lVT l or lβVSAT l = lβVSAT l where β is the feedback ratio.
R1  R 2
PROCEDURE:
1. Calculate the value of components using the design procedure given.
3. As there is no specific input signal for this circuit switch ON the power supply.
4. Note down the reading for output square wave (i.e.) time & amplitude and tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
33
CIRCUIT DIAGRAM - (ASTABLE):-
R=47K
+15v
0.01uf
2 - 7
IC 741
6 R2=22K
3 + 4
Vc +
CRO CRO Channel 1
Channel 2
-
Vref R1=10K
TABULATION:
Amplitude(V) Time(T)
Sl.No Waveform
Volts ms
1 Capacitor
2 Output
MODEL GRAPH:
VC
± VSat – Saturation Voltage

± Vt – Threshold Voltage
34
CIRCUIT DIAGRAM - (MONOSATBLE):

Rf=R3=47K
+15v
2 7
- R3=10K
IC 741
6
C=0.01uf D1 3 + 4
R1=10K
-15V
+
D2 CRO
C1=0.1uf -
R2=10K
Triggering
R4=100Ω
Input
Vin
TABULATION:
Amplitude Time period

S.No Waveforms
(volts) (ms)
1. Input waveform(Trigger)
2. Output waveform
MODEL GRAPH:
INPUT
Trigger
Input TIME (ms)
AMPLITUDE
OUTPUT
Square
Wave
Output TIME (ms)
35
DESIGN PROCEDURE:
1. Assume R1 = R2 = 10KΩ & calculate β from expression

R1 10 K
β= = = 0.5.
R1  R 2 20 K
2. Find the value of R & C from the pulse width time expression.
(1  VD / Vsat )
T = RC ln
1 
(1  VD / Vsat )
T = RC ln
0.5
T ≡0.69RC.
3. Assume C = 0.01μf and R = 50KΩ ≈ 47KΩ. Find T where Rf = R & R3=10K

T = 0.69 (50X103) (0.01X10-6)
T = 0.345ms.
4. Triggering pulse width Tp must be much smaller than T. Tp < T.
5. Assume a HPF in the input session with C1=0.1μf (Assumption) & R4 = 100Ω.
PROCEDURE:
1. Calculate the value of components using the design procedure given.
3. Apply the negative trigger voltage to the non-inverting terminal.
4. Note down the reading for output voltage Vo & ON & OFF time period & tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
SCHMITT TRIGGER:-
CIRCUIT DIAGRAM:-
+15v
ROM=R1//R2 2 7
-
10KΩ IC 741 6
3 + 4
+
-15V RL=10K +
Vin ~ CRO
R2=100K -
R1
10K
36
TABULATION:
Voltage(V) Time(T)
Sl.No Signal
Volts ms
1 Input Signal
2 Output Signal
MODEL GRAPH:
37
DESIGN PROCEDURE:-
1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity. Let Vut = 1V
& Vlt = -1V.
2. For Op-amp 741C ± Vsat ≡ ±13V to ± 14V. And assume Vref = 0, Since the another end of
R1 is grounded.
3. if Vo = +Vsat the voltage at the positive terminal will be (voltage from potential divider
R1 & R2).
R1
Vut = Vref + (Vsat - Vref)
R1  R2
Therefore Vref = 0.
R1
Vut = (+ Vsat).
R1  R2
R1
4. Similarly Vlt will be Vlt = ( ) – Vsat.
R1  R2
5. Sub Vut & assume R1 or R2 & find the other component value.
R1
1V = (13)
R1  R2
R1 + R2 = 13R1
R2 = 12R1 if R1 = 10K then R2 = 120K ≡100K.

6. Calculate ROM by
R1R2 (10 K)(100 K)
ROM = R1 // R2 = .
R1  R2 110 K
1000 K
ROM = ≡ 10KΩ. & select RL = 10KΩ (Assumption)
110 K
7. Calculate hystersis voltage
Vhy = Vut – Vlt
R1
= [+Vsat – (-Vsat)]
R1  R2
10 K
= [26V] Since Vsat = 13V
110 K
= 0.0909 [26V]
Vhy = 2.363V
38
PROCEDURE:
1. Design the value of circuit components and select VUT & VLT as given in the design
procedure.
3. Apply the input signal to the input terminal of op-amp & set VUT & VLT values.
4. Note down the readings from the output waveform.
5. Plot the graph & show the relationship between Input sine wave & Output square wave.
RESULT:
Thus an Astable, Monostable multivibrator and Schmitt trigger are designed and
tested using op-amp IC 741.
39
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR

EXP.NO: 06 USING OP-AMP
AIM:
To design RC Phase Shift and Wien Bridge Oscillator using Op-amp IC 741 and
to test its performance.
APPARATUS REQUIRED:

1. IC 741 --- 01
1.5KΩ 3.3KΩ, 33KΩ, EACH 03
2. RESISTORS
10 KΩ 22 KΩ, 1MΩ, EACH 01
3. CAPACITORS 0.1μf 03
DESIGN PROCEDURE:
Design a RC phase shift oscillator to oscillate at 200Hz.

1. Select fo = 200Hz.
2. Assume C = 0.1μf & determine R from fo.
1 1
fo = =R= = 3.3K.
2 6 RC 2 6 f oc
3. To prevent the loading of amp because it is necessary that R1>>10R.
Therefore R1=10R=33K.
4. At this frequency the gain must be atleast 29 (i.e.) Rf / R1 =29.
Therefore Rf = 29R1.
Rf = 29 (33K) = 957KΩ.
Therefore use Rf = 1MΩ.
40
RC PHASE SHIFT OSCILLATOR:-

CIRCUIT DIAGRAM:-
Rf=1MΩ
+15v
R1=33K 2 - 7
IC 741
+ 6
3 4
R1//Rf(or)ROM 33K -15v
+
CRO
C=0.1μf C=0.1μf0 C=0.1μf
-
R=3.3K R=3.3K R=3.3K
TABULATION:.
OBSERVED OUTPUT WAVEFORM
Amplitude Time period Frequency Design Frequency

(volts) (ms) (Hz) (Hz)
MODEL GRAPH:
Vout
OUTPUT Time (ms)
41
WIEN BRIDGE OSCILLATOR:-

CIRCUIT DIAGRAM:-
R1=10K Rf=22K
+15v
2 - 7
IC 741
+ 6
3 4
R=1.5K C=0.1uf
-15v +
CRO
R=1.5K -
C=0.1uf
TABULATION:
OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)
MODEL GRAPH:
Vout
OUTPUT Time (ms)
42
PROCEDURE- (RC PHASE SHIFT):-

1. Select the given frequency of oscillation f0 = 200Hz.
1
2. Assume either R or C to find out the other using formula f0 = .
2 6 RC
3. The gain is selected such that Rf / R1 = 29K. Assume Rf or R1 to find the other.
5. Measure the amplitude frequency of the output signal plot the graph.
DESIGN PROCEDURE:
(i) Select frequency f0 = 1 KHz.

1
(ii) Use f0 = , A = 1+ (Rf / R1) = 3. To find R & Rf.
2RC
(iii) Therefore Rf = 2R1 & assume C = 0.1μf & find R from
1
R= = 1.59KΩ.
2f o C
(iv) Assume R1 = 10K & find Rf from Rf = 2R1
Therefore Rf = 20K ≡ 22KΩ
PROCEDURE:
1. Select the given frequency of oscillation f0 = 1 KHz.
1
2. Assume either R or C to find out the other using formula . Also determine the
2RC
value of other components as given in design procedure.
4. Measure the amplitude and frequency of the output signal to plot the graph.
RESULT:
Thus RC Phase Shift and Wien Bridge Oscillator were designed and tested using
op-amp IC 741.
43
PIN CONFIGURATION OF 555 TIMER IC
Features of 555 IC:-

1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or
Between pin 3 & VCC (supply)
2. 555 can be reset by applying negative pulse, otherwise reset can be connected to +V cc to
avoid false triggering.
3. An external voltage effects threshold and trigger voltages.
4. Timing from micro seconds through hours.
5. Monostable and bistable operation
6. Adjustable duty cycle
7. Output compatible with CMOS, DTL, TTL
8. High current output sink or source 200mA
9. High temperature stability
10. Trigger and reset inputs are logic compatible.
Specifications:-
1. Operating temperature : SE 555-- -55oC to 125oC
NE 555-- 0o to 70oC
2. Supply voltage : +5V to +18V
3. Timing : μSec to Hours
4. Sink current : 200mA
5. Temperature stability : 50 PPM/oC change in temp or 0-005% /oC.
Applications:-
1. Monostable and Astable Multivibrator
2. dc-ac converters
3. Digital logic probes
4. Waveform generators
5. Analog frequency meters
6. Tachometers
7. Temperature measurement and control
8. Infrared transmitters
9. Regulator & Taxi gas alarms etc.
44
Block Diagram of IC 555:
Function of Various Pins of 555 IC:

Pin (1) of 555 is the ground terminal; all voltages r measured with respect to this pin.
Pin (2) of 555 is the trigger terminal, If the voltage at this terminal is held greater than one-third
of VCC, the output remains low. A negative going pulse from Vcc to less than Vec/3 triggers the
output to go high. The amplitude of the pulse should be able to make the comparator (inside the
IC) change its state. However the width of the negative going pulse must not be greater than the
width of the expected output pulse.
Pin (3) is the output terminal of IC 555. There are 2 possible output states. In the low output
state, the output resistance appearing at pin (3) is very low (approximately 10 Ω). As a result the
output current will goes to zero , if the load is connected from Pin (3) to ground , sink a current I
Sink (depending upon load) if the load is connected from Pin (3) to ground, and sinks zero current
if the load is connected between +VCC and Pin (3).
Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the potential of
Pin (4) is drives below 0.4V, output is immediately forced to low state. The reset terminal
enables the timer over-ride command signals at Pin (2) of the IC.
Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels at which the
time comparators change state. A resistor connected from Pin (5) to ground can do the job.
Normally 0.01μF capacitor is connected from Pin (5) to ground. This capacitor bypasses supply
noise and does not allow it affect the threshold voltages.
Pin (6) is the threshold terminal. In both Astable as well as Monostable modes, a capacitor is
connected from Pin (6) to ground. Pin (6) monitors the voltage across the capacitor when it
charges from the supply and forces the already high O/p to Low when the capacitor reaches +2/3
VCC.
Pin (7) is the discharge terminal. It presents an almost open circuit when the output is high and
allows the capacitor charge from the supply through an external resistor and presents an almost
short circuit when the output is low.
Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V.
45
ASTABLE & MONOSTABLE MULTIVIBRATOR

EXP.NO: 07
USING IC 555 TIMER
AIM:
To Design and test Astable and Monostable multivibrator using 555 timer IC.
APPARATUS REQUIRED:

1. IC 555 --- 01
2. RESISTORS 3.3KΩ, 6.8KΩ, 10KΩ. EACH 01
3. CAPACITORS 0.1μf, 0.01μf. EACH01

PROCEDURE:
1. Calculate the component values using the design procedure.
3. Observe and note down the output waveform.
4. Measure the frequency of oscillations and duty cycle and then compare with the given
values.
5. Plot both the waveforms to the same time scale in a graph.
46
CIRCUIT DIAGRAM - (ASTABLE):
HI
6.8K +5V
RA
3.3K 7 8 4 3
RB IC 555
5
6 2 1 +
CRO Vo
-
Vc C=0.1μf 0.01uf
TABULATION:
Amplitude(V) Time(T)
Sl.No Waveform
Volts ms
1 Capacitor
2 Output
MODEL GRAPH:
(a) Square wave output

(b) Capacitor voltage of Square wave output
47
DESIGN PROCEDURE:-
Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 30% using 555
timer IC.
Given Frequency=1000Hz
Duty cycle=30%
D= T low/T high = RB/(RA+2RB)*100 ----------------------------------- (1)
T high =0.69(RA+RB) C
T low = 0.69 RBC
From equation 1
0.30 T high = T low
0.30 * 0.69(RA+RB)C = 0.69 RBC
0.207(RA+RB)C = 0.69 RBC
0.483 RB-0.207 RA= 0 ------------------------------------------------- (2)
Given f=1 kHz we know that T=1/f

T=1ms
T= T high + T low
0.69(RA+RB) C +0.69 RBC= 1ms.
0.69(RA+RB) +0.69 RB = 1ms/C
Let C=0.1μF
0.69RA+0.69RB +0.69 RB = 1ms./0.1*10-6
0.69RA+1.38RB = 10 4 ------------------------------------------------ (3)
Solving equation 2 & 3 we get

RA=6.8K
RB= 2.674K≡3.3KΩ
48
MONOSATBLE MULTIVIBRATOR:- CIRCUIT DIAGRAM:-
HI
+5V
RA
10K
7 8 4 3
IC 555
5
6 2 1 +
C
0.1uf CRO Vo
Vc
Trigger -
Input
0.01uf
Vin
TABULATION:
Amplitude Time period

S.No Waveforms
(volts) (ms)
1. Input waveform
2. Output waveform
Capacitive waveform
3.
(Capacitor voltage Vc)
MODEL GRAPH:
49
DESIGN PROCEDURE:-
Let, RA = 10K
Out put pulse width tp = 10μs
tp = 1.1RAC
C= 0.909μF
C=0.1μF
PROCEDURE:-
1. Calculate the value of R & C using design procedure.
3. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
4. Observe the output waveform and measure the pulse duration.
5. Theoretically calculate the pulse duration as T high=1.1 RAC
RESULT:
Thus the Astable and Monostable multivibrator is designed and tested using 555 timer IC
50
PLL IC 565
THEORY:-
The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE 560, 561,
562, 564, 565, & 567 differ mainly in operating frequency range, power supply requirements and
frequency and bandwidth adjustment ranges. The device is available as 14 Pin DIP package and
as 10-pin metal can package. Phase comparator or phase detector compare the frequency of
input signal fs with frequency of VCO output fo and it generates a signal which is function of
difference between the phase of input signal and phase of feedback signal which is basically a
d.c voltage mixed with high frequency noise. LPF remove high frequency noise voltage. Output
is error voltage. If control voltage of VCO is 0, then frequency is center frequency (f o) and mode
is free running mode. Application of control voltage shifts the output frequency of VCO from f o
to f. On application of error voltage, difference between fs & f tends to decrease and VCO is said
to be locked. While in locked condition, the PLL tracks the changes of frequency of input signal.
Block Diagram of IC 565
PROCEDURE:
1. Determine the component values using the design procedure given here.
2. Connect the components as shown in the circuit diagram.
3. Note down the readings of output waveform with respect to input signal.
51
Pin Configuration:
Specifications:
1. Operating frequency range : 0.001 Hz to 500 KHz
2. Operating voltage range : ±6 to ±12V
3. Inputs level required for tracking : 10mV rms minimum to 3v (p-p) max.
4. Input impedance : 10 KΩ typically
5. Output sink current : 1mA typically
6. Drift in VCO center frequency : 300 PPM/oC typically
(fout) with temperature
7. Drif in VCO centre frequency with : 1.5%/V maximum
supply voltage
8. Triangle wave amplitude : typically 2.4 VPP at ± 6V
9. Square wave amplitude : typically 5.4 VPP at ± 6V
10. Output source current : 10mA typically
11. Bandwidth adjustment range : <±1 to >± 60%
Center frequency fout = 1.2/4R1C1 Hz
= free running frequency
FL = ± 8 fout/V Hz
V = (+V) – (-V)

fc = ± 
fL
1 / 2
 2(3.6) x10 xC2
3
Applications:
1. Frequency multiplier
2. Frequency shift keying (FSK) demodulator
3. FM detector
52
CIRCUITDIAGRAM
NE 565 PLL connection diagram
DESIGN PROCEDURE:-
If C= 0.01μF and the frequency of input trigger signal is 2KHz, output pulse width of 555
in Monostable mode is given by
1.1RAC = 1.2T =1.2/f
RA= 1.2/(1.1Cf)=54.5KΩ
fIN=fOUT/N
Under locked conditions,
fOUT = NfIN = 2fIN = 4KHz
53
PLL CHARACTERISTICS AND FREQUENCY

EXP.NO: 08
MULTIPLIER USING PLL
AIM:
To design & test the characteristics of PLL and to construct and test frequency multiplier
using PLL IC565.
APPARATUS REQUIRED:
S.NO COMPONENTS / EQUIPMENT VALUE QUANTITY

1 IC 565 --- 01
2 IC 555 --- 01
3 RESISTORS 12KΩ, 54.5 KΩ, 6.8K Each one
0.01μF 4
CAPACITORS
4
0.1 μf, 10μf, 1 μf EACH 01
5 DIGITAL TRAINER KIT --- 01
6 REGULATED POWER SUPPLY (0 -30V), 1A 1

7 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1
8 CONNECTING WIRES --- FEW
54
PLL as Frequency Multiplier
(a) : Input
(b) : PLL output under locked conditions without 555
(c) : Output at pin4 of 565 with 555 connected in the feedback
55
THEORY:
The frequency divider is inserted between the VCO and the phase comparator of PLL.
Since the output of the divider is locked to the input frequency fIN, the VCO is actually running
at a multiple of the input frequency .The desired amount of multiplication can be obtained by
selecting a proper divide– by – N network ,where N is an integer. To obtain the output frequency
fOUT=2fIN, N = 2 is chosen. One must determine the input frequency range and then adjust the
free running frequency fOUT of the VCO by means of R1 and C1 so that the output frequency of
the divider is midway within the predetermined input frequency range. The output of the VCO
now should be 2fIN . The output of the VCO should be adjusted by varying potentiometer R 1. A
small capacitor is connected between pin7 and pin8 to eliminate possible oscillations. Also,
capacitor C2 should be large enough to stabilize the VCO frequency.
SAMPLE READINGS:
PARAMETER INPUT OUTPUT
Amplitude (Vp-p)
Frequency (KHz)
PROCEDURE:-
1. The circuit is connected as per the circuit diagram.
2. Apply a square wave input to the pin2 of the 565
3. Observe the output at pin4 of 565 under locked condition.
4. Give the output of 565 to the pin2 of 555 IC.
5. Observe the output of 555 at pin3.
6. Now give the output of 555 as feedback to the pin5 of the 565.
7. Observe the frequency of output signal fo at pin4 of 565 IC.
8. Plot the waveforms in graph.
RESULT:
Thus the PLL characteristics are designed and tested and Frequency multiplier using IC
565 is constructed and tested.
56
EXP.NO: 09 R-2R LADDER TYPE D- A CONVERTER USING OP-AMP
AIM:
To design a 4-bit R-2R ladder type DAC using OP-AMP.
APPARATUS REQUIRED:
S.NO COMPONENTS / EQUIPMENT VALUE QUANTITY

1 IC 741 --- 01
2 RESISTOR 22K, 10K 05, 04
3 DIGITAL MULTIMETER METER
4 DIGITAL TRAINER KIT --- 01
5 REGULATED POWER SUPPLY (0 -30V), 1A 1

6 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1
7 CONNECTING WIRES --- FEW
THEORY:
In R-2R ladder network only two values of resistors are required. Consider 4
bit DAC, where switch position d1,d2,d3,d4 corresponding to binary words.
PROCEDURE:
1. Connections are made as per the circuit diagram.

2. The inputs are given through b0,b1,b2,b3.
3. The inputs are given from (0-15)V and observe the outputs in voltmeter.
4. The graph is drawn.
57
CIRCUIT DIAGRAM:
TABULATION:
Equivalent Binary Practical Theoretical

Decimal Voltage Voltage
(V) (V)
b3 b2 b1 b0
58
DESIGN PROCEDURE:
Vo = -Rf (b3/2R + b2/4R + b1/8R + b0/16R)Vref
Rf = R
Vo = -Vref (b3/2 + b2/4 + b1/8 + b0/16)
Assume R = 10K
2R = 22K
RESULT:
Thus the 4-bit R-2R ladder type DAC is designed and its outputs are verified.
59
EXP.NO: 10 DC POWER SUPPLY USING LM317 AND LM723
AIM:
To design and test the power supply voltage regulator using LM317 and LM723 ICs.
APPARATUS REQUIRED:

1. LM317 and LM723 --- EACH 01
30Ω, 100Ω, 1KΩ,

2. RESISTORS EACH 01
3.3KΩ, 220Ω,

4. ANALOG VOLTMETER (0-10)V 01
5. DUAL POWER SUPPLY (0-30)V 01
PIN DIAGRAM:
60
CIRCUIT DIAGRAM - (LM723):
Vin (0-30) V
HI Vref=5V HI
12 11
R4=100E
6 10 Vo
R1=1K
IC 723 2
5
R2=3.3K 3
R3=33E
7
13 4
C=220pf
TABULATION:
INPUT VOLTAGE OUTPUT VOLTAGE

S.NO
(Volts) (Volts)
1.
2.
3.
4.
5.
6.
7.
8.
61
MODEL GRAPH:
CHARACTERISTICS OF THE LM317HVK:
The LM317HVK will provide a regulated output current of upto 1.5A,Provided that if is
not subjected to a power dissipation of more than about 15W.This means it should be electrically
isolated from, and fastened to, a large heat sink such as the metal chassis of the power supply.
The LM317 requires a minimum “dropout” voltage of 3v across its input and output
terminals or it will drop out of regulation. Thus the upper limit of Vo is 3V below the minimum
input voltage from the unregulated supply.
It is good practice to connect bypass capacitors .This reduces the ripple voltage from the
rectifier.
The LM317HVK protects itself against over heating, too much internal power dissipation
and too much current. When the chip temperature reaches 175 degrees, the 317 shuts down. If
the product of output current and input-to-output voltage exceeds 15 to 20W, or if currents
greater than about 1.5A are required the LM317 also shuts down. When the overload condition is
removed the Operation is resumed. All these features are made possible by the remarkable
internal circuitry of LM317.
Along with the simple 3 pin fixed regulators; a number of adjustable or programmable
devices are available. Some devices also include features such as programmable current limiting.
It is also possible to configure multiple regulators so that they track or follow each other.
62
DESIGN PROCEDURE: (IC723)

Given :
Vref = 5v
Vo = 4v
We know that
Vo = Vref (R2/ (R1+R2))
4R1+4R2=5R2
R2=4R1
Let R1=1k
R2=4K ≈ 3.3KΩ
PIN DIAGRAM:
CIRCUIT DIAGRAM - (LM317):
3 2
63
MODEL GRAPH:
TABULATION:
INPUT VOLTAGE OUTPUT VOLTAGE

S.NO
(Volts) (Volts)
PROCEDURE:
1) Connections are made as per the circuit diagram.
2) The reference voltage of 5v is set and the input voltage is varied between (0-30) v
3) The corresponding output is taken using voltmeter.
4) The readings are tabulated and the graph is plotted.
RESULT:
The 723 & 317 IC voltage regulators are designed and the regulation of supply voltage was
tested.
64
EXP NO : 11 STUDY OF SMPS
AIM:
To study the control of SMPS
THEORY:
The switching regulator is also called as switched mode regulator. In this case, the
pass transistor is used as a controlled switch and is operated at either cutoff or saturated state.
Hence the power transmitted across the pass device is in discrete pulses rather than as a steady
current flow. Greater efficiency is achieved since the pass device is operated as a low impedance
switch. When the pass device is at cutoff, there is no current and dissipated power. Again when
the pass device is in saturation, a negligible voltage drop appears across it and thus dissipates
only a small amount of average power, providing maximum current to the load. The efficiency is
switched mode power supply is in the range of 70-90%.
A switching power supply is shown in figure. The bridge rectifier and capacitor
filters are connected directly to the ac line to give unregulated dc input. The reference regulator
is a series pass regulator. Its output serves as a power supply voltage for all other circuits. The
transistors Q1, Q2 are alternatively switched ‘on’ &; off, these transistors are either fully ‘on’ or
‘cut-off, so they dissipate very little power. These transistors drive the primary of the main
transformer. The secondary is centre tapped and full wave rectification is achieved by diodes D1
and D2. This unidirectional square wave is next filtered through a two stage LC filter to produce
output voltage Vo.
SG 3524:
FUNCTION:
Switched Mode Power Supply Control Circuit
FEATURES:
 Complete PWM Power Controlled circuitry.
 Single ended or push-pull outputs.
 Line and Load regulation of 0.2%.
 1% maximum temperature variation.
 Total Supply current is less than 10mA
 Operation beyond 100KHz
65
PIN DETAILS:
PIN NO. FUNCTION

1 Inverting input
2 Non Inverting input
3 Oscillator output
4 (+)CL sense
5 (-)CL sense
6 RT
7 CT
8 Ground(-ve supply voltage)
9 Compensation
10 Shutdown
11 Emitter-A
12 Collector-A
13 Collector-B
14 Emitter-B
15 Vin
16 Vref
TECHNICAL INFROMATION:
TEMPERATURE
DESCRIPTION
RANGE
SG3524N(16-pin plastic DIP) 0C to 70C
SG3524F(16-pin cerdip) 0C to 70C
SG3524D(16-pin SO) 0C to 70C
66
67
RESULT:
Thus the control of SMPS IC SG3524 had been studied.
68
SIMULATION OF ACTIVE LOWPASS, HIGH PASS AND BAND PASS

EXP.NO: 12
FILTER USING PSPICE
AIM:
To simulate and analyze the Active Low pass, High pass and Band pass
Filters using PSPICE.
SOFTWARE REQUIRED:
SPICE SOFTWARE
PROCEDURE:
 Switch on the computer and select PSPICE icon.


 Open a new project to design a circuit in the file menu.

 Select the required components from the library.

 Draw the circuit as shown in Fig (1) &(2) tool bar.

 After completing save the project and go to simulation tool bar

 Verify the simulated output and take a print out.
69
CIRCUIT DIAGRAM-(FILTERS):
LOWPASS FILTER
70
RESULT:
Thus the Active Low pass, High pass and Band pass Filters using
PSPICE was simulated and tested.
71
SIMULATION OF ASTABLE AND MONOSTABLE MULTI VIBRATOR

EXP.NO: 13
USING IC555 TIMER
AIM:
To simulate and analyze the Astable and monostable multivibrators using

NE555 Timer using PSPICE.
SOFTWARE REQUIRED:
SPICE SOFTWARE
PROCEDURE:
 Switch on the computer and select PSPICE ion.


 Open a new project to design a circuit in the file menu.

 Select the required components from the library.

 Draw the circuit as shown in Fig (1) &(2) tool bar.

 After completing save the project and go to simulation tool bar

 Verify the simulated output and take a print out.
72
CIRCUIT DIAGRAM-(ASTABLE MULTIVIBRATOR):
MODEL GRAPH:
73
CIRCUIT DIAGRAM-(MONOSTABLE MULTIVIBRATOR):
SIMULATION OUTPUT:
74
RESULT:
Thus the Astable and Monostable Multivibrators using NE555 Timer

using PSPICE was simulated and tested.
75
SIMULATION OF ADC,DAC AND ANALOG

EXP.NO: 14
MULTIPLIER USING PSPICE
AIM:
To simulate and analyse the ADC, DAC& Anolog Multiplier using
PSPICE.
SOFTWARE REQUIRED:
SPICE SOFTWARE
PROCEDURE:
 Switch on the computer and select PSPICE ion.


 Open a new project to design a circuit in the file menu.

 Select the required components from the library.

 Draw the circuit as shown in Fig (1) &(2) tool bar.

 After completing save the project and go to simulation tool bar

 Verify the simulated output and take a print out.
76
CIRCUIT DIAGRAM-(ANALOG TO DIGITAL CONVERTER):
CIRCUIT DIAGRAM-(DIGITAL TO ANALOG CONVERTER):
77
ANALOG MULTIPLIER :
RESULT:
Thus the ADC, DAC, & Anolog Multiplier using PSPICE was simulated and
tested.
78
EC6412-Linear Integrated Circuits. Lab Dept of Electronics & Communication Engg
CONTENT BEYOND THE SYLLABUS
EXP.NO:15 CHARACTERISTICS OF OP-AMP
AIM:
To measure the following parameters of op-amp
1. Input bias current
2. Input offset current
3. Input offset voltage
4. Slew rate
APPARATUS REQUIRED:
S.No. APPARATUS TYPE RANGE QUANTITY
1) Op-Amp
2) Resistors
3) Capacitors
4) Signal Generator
5) CRO
6) Dual power supply
7) Bread Board
8) Connecting wires
THEORY:
Input bias current: The inverting and noninverting terminals of an op-amp are
actually two base terminals of transistors of a differential amplifier. In an ideal op-amp
it is supported that no current flows through these terminals. However, practically a
small amount of current flows through these terminals which is on the order of nA
(typical and maximum values are 80 and 1500nA) in bipolar op-amps and pA for FET
op-amps. Input bias current is defined as the average of the currents entering into the
inverting and noninverting terminals of an op-amp.
Input offset current: The bias currents IB1 and IB2 will not be equal in an op-amp. Input
offset current is defined as the algebraic difference between the currents into the
inverting and non-inverting terminals. I OS input offset current are 20nA and 200nA.
bias currents of the op-amp.
 I B1  I B 2
Input offset voltage: Even if the input voltage is zero, output voltage may not
be zero. This is because of the circuit imbalances inside the op-amp. In order to
compensate this, a small voltage should be applied between the input terminals. Input
offset voltage is defined as the voltage that must be applied between the input terminals
of an op-amp to nullify the output voltage. Typical and maximum values of input offset
DMI College Of Engineering 79

voltage are 2mV and 6mV.
Slew rate: Slew rate is the rate of rise of output voltage. It is the measure of
fastness of op-amp. It is expressed in V/μsec. If the slope requirements of the output
voltage of the op-amp are greater than the slew rate, distortion occurs. Slew rate is
measured by applying a step input voltage.
PROCEDURE:
a) Input Bias Current

1. Connect the circuit as shown in Fig.1.1.
2. Measure the output voltage from which the inverting input bias current can
be calculated as IB- = Vo/Rf.
4. Measure the output voltage from which the non-inverting input bias
current can be calculated as IB+ = Vo/Rf.
5. Average of magnitude of both IB- and IB+ gives the input bias current.
b) Input Offset Current

2. Measure the output voltage using multimeter.
3. Calculate the offset current as Ios = Vo/Rf.
c) Input Offset Voltage

2. Measure the output voltage using multimeter
3. Calculate offset voltage as Vos = Vo / (1+ Rf / R1).
d) Slew Rate
2. Give square wave input from the signal generator so that the output is a
square wave at 1kHz.
3. Increase the frequency slowly until the output is just barely a
triangular wave.
V 
4. Calculate slew rate as SR = ( / t).
PIN DIAGRAM:

CIRCUIT DIAGRAM:
To measure input offset voltage

+1 5V
7
3
+
6
74 1 Vo
2
-
4
-15V
Ri Rf
4.7 k 100 k
To measure input bias current

To measure input offset current
+15V
7
3
+
6
741 Vo
2
-
4
-15V
1M
C
0.01
To measure slew rate

+15V 7
3
+
1
741 6 Vo
2 -
Vin
4
-15V
2
TYPICAL VALUES OF ELECTRICAL CHARACTERISTICS OF A741:

Input bias current = 80-500nA
Input offset current = 20-200nA
Input offset voltage = 1-5mV
Slew rate = <0.5 V/s
RESULT:
The input bias current, input offset current, input offset voltage and slew rate
of the op-amp were determined.
Input offset voltage = ……..mV
Input bias current = ……..A
Input offset current = ...…...A
Slew rate = ……..V/μs.

EXP.NO:16 APPLICATIONS OF OP-AMP
AIM:
To demonstrate the use of op-amp as summing amplifier and Subtractor using
Op-amp 741.
APPARATUS REQUIRED:
APPARATUS TYPE RANGE QUANTITY
S.No.
1) Op-Amp
2) Resistors
4) Signal Generator
5) CRO
6) Dual power supply
7) Bread Board
8) Connecting wires
THEORY:
Summing Amplifier: Op-amp may be used to perform summing operation of
several input signals in inverting in inverting and non-inverting mode. The input signals
to be summed up are given to inverting terminal or non-inverting terminal through the
input resistance to perform inverting and non-inverting summing operations
respectively.
Subtractor: The basic difference amplifier can be used as a subtractor. The

signals to be subtracted are connected to opposite polarity inputs i.e. in inverting or non-
inverting terminals of the op-amp.
PROCEDURE:
a) Inverting summing amplifier:
1. Connect the circuit as shown in figure
2. Connect batteries for voltage V1, V2.
3. Measure and note the output voltage and compare it with theoretical
value Vo = -(Rf / Ri) (V1+V2)
b) Subtractor:
4. Connect the circuit as shown in figure
5. Measure and note the output voltage and compare it with theoretical

value.
PIN DIAGRAM:
CIRCUIT DIAGRAM:
SUMMING AMPLIFIER:
TABULATION:
S.No. V1 V2 Theoretical Practical

V0=V1+V2 V0

SUBTRACTOR:
TABULATION
S.No. V1 V2 Theoretical Practical

V0=V1-V2 V0
RESULT:
Thus the use of op-amp as summing amplifier, subtractor, was studied.

EC8462

Uploaded by

Copyright:

Available Formats

EC8462

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

EC8462

Uploaded by

Copyright:

Available Formats

DMI COLLEGE OF ENGINEERING

PALANCHUR CHENNAI – 600 123

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

SUB CODE : EC8462

Vision of the Department

To develop committed and competent technologists in electronics and communication

PROGRAM EDUCATIONAL OBJECTIVES (PEOs):

PEO1. CORE COMPETENCY WITH EMPLOYABILITY SKILLS: Building on

PROGRAM OUTCOMES (POs)

The Program Outcomes (POs) are described as.

1. Engineering Knowledge: Apply the knowledge of mathematics, science,

10. Communication: Communicate effectively on complex engineering activities with

PROGRAM SPECIFIC OUTCOMES (PSOs):

PSO2. Implement functional blocks of hardware-software co-designs for signal

INSTRUCTIONS TO STUDENTS FOR WRITING THE RECORD

On the right side page of the record following has to be written:

On the Left side page of the record following has to be recorded:

for selecting the components should be clearly shown if necessary.

i) Data should be clearly recorded using Tabular Columns.

ii) Unit of the observed data should be clearly mentioned

EC8462 LINEAR INTEGRATED CIRCUITS LABORATORY LT PC

SIMULATION USING SPICE

CO 1 Design oscillators and amplifiers using operational amplifiers

CO 2 Design filters using Opamp and perform experiment on frequency response

CO 3 Analyse the working of PLL and use PLL as frequency multiplier

CO 4 Design DC power supply using ICs.

CO 5 Analyse the performance of oscillators and multivibrators using SPICE

CO , PO, PSO Mappings

Average 3 2.2 2 2.4 3 3 - - 3 3 - 2 3 3 3

EX.No. LIST OF THE EXPERIMENT PAGE NO

INVERTING, NON-INVERTING AND DIFFERENTIAL

2 INTEGRATOR AND DIFFERENTIATOR USING OP-AMP 16

ACTIVE LOW PASS, HIGH PASS AND BAND PASS FILTER

ASTABLE, MONOSTABLE MULTIVIBRATOR AND

RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR

ASTABLE & MONOSTABLE MULTIVIBRATOR

PLL CHARACTERISTICS AND FREQUENCY

9 R-2R LADDER TYPE D- A CONVERTER USING OP-AMP. 57

10 DC POWER SUPPLY USING LM317 AND LM723 60

EX.No. LIST OF THE EXPERIMENT PAGE NO

SIMULATION OF ACTIVE LOWPASS, HIGH PASS AND

SIMULATION OF ASTABLE AND MONOSTABLE

SIMULATION OF ADC,DAC AND ANALOG

CONTENT BEYOND THE SYLLABUS

IC 741 - General Description:

Block Diagram of Op-Amp:

INVERTING, NON-INVERTING AND DIFFERENTIAL

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

PROCEDURE-(INVERTING & NON-INVERTING AMPLIFIER):-

Vin1 Vin2 Vin2 - Vin1 V0 Theoretical Gain Practical Gain

EXP.NO: 02 INTEGRATOR AND DIFFERENTIATOR USING OP-AMP

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

(i) FOR SINE WAVE INPUT

SINE WAVE INPUT:

EXP.NO: 03 INSTRUMENTATION AMPLIFIER

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

COMMON MODE GAIN CALCULATION - AC

DIFFERENTIAL MODE GAIN - AD & CMRR CALCULATION.

EXP.NO: 04 ACTIVE LOW PASS, HIGH PASS AND BAND PASS