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file: my_capacitor.va
`include "constants.h" `include "discipline.h" module my_capacitor (t1,t2); inout t1,t2; electrical t1,t2,n1,n2; //Branch definitions branch (t1,n1) br_cap; branch (n1,n2) br_rser; branch (n2,t2) br_lser; //Parameter initialization parameter real c = 1; parameter real rser = 0; parameter real lser = 0; analog begin I(br_cap) <+ c*ddt(V(br_cap)); V(br_rser) <+ rser*I(br_rser); V(br_lser) <+ lser*ddt(I(br_lser)); end endmodule
file: test_my_capacitor.spice
.title my_capacitor.osdi test v1 n01 0 dc 0 ac 1 n1 n01 0 c_10nF .model c_10nF my_capacitor c=10n rser=10m lser=1n .control pre_osdi my_capacitor.osdi ac dec 100 1Meg 1000Meg let z=abs(v(n01)/i(v1)) settype impedance z plot xlog ylog z .endc .end
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file: my_capacitor.va
`include "constants.h" `include "discipline.h" module my_capacitor (t1,t2); inout t1,t2; electrical t1,t2,n1,n2; //Branch definitions branch (t1,n1) br_cap; branch (n1,n2) br_rser; branch (n2,t2) br_lser; //Parameter initialization parameter real c0 = 1; parameter real v0 = 1; parameter real rser = 0; parameter real lser = 0; real q; analog begin //DC bias characteristics of ceramic capacitors q = c0*v0*atan(V(br_cap)/v0); I(br_cap) <+ ddt(q); V(br_rser) <+ rser*I(br_rser); V(br_lser) <+ lser*ddt(I(br_lser)); end endmodule
file: test_my_capacitor.spice
.title my_capacitor.osdi test v1 n01 0 dc 0 ac 1 n1 n01 0 c_10nF .model c_10nF my_capacitor c0=10n v0=15 rser=10m lser=1n .control pre_osdi my_capacitor.osdi let v=0 let vstop=20 let vstep=10 while v <= vstop alter v1 dc v $ ac analysis ac dec 100 1Meg 1000Meg let v=v+vstep end * calculate impedance let z1=abs(1/ac1.i(v1)) let z2=abs(1/ac2.i(v1)) let z3=abs(1/ac3.i(v1)) * color0 i background, color1 is grid & text color, color2..22 are for graph plots set color0=white color1=gray color2=red color3=blue color4=green color5=black set wfont='DejaVu Sans Mono' set wfont_size=12 set xbrushwidth=2 plot z1 z2 z3 xlog ylog .endc .end
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