ã«ãã´ãªã¤ã³ããã¯ã¹ï¼https://msyksphinz.hatenablog.com/entry/2024/12/14/040000
ã¾ãã¯åºæ¬çãªãã©ã¼ãã«ãåå¼·ããããã«ãSymbiYosysã使ã£ã¦ALUãæ¤è¨¼ãã¦ã¿ããã 以ä¸ã«Half Adder & Half Adder & ALUãæ§æãããã¶ã¤ã³ãä½ã£ãã
ha.v
module ha // éä¸çç¥ endmodule // ha
fa.v
module fa // éä¸çç¥ endmodule // fa
alu.v
module alu ( input logic [ 7: 0] a, input logic [ 7: 0] b, output logic [ 8: 0] s ); logic [ 7: 0] c; fa fa0 (.a(a[0]), .b(b[0]), .cin(1'b0), .s(s[0]), .cout(c[0])); generate for (genvar idx = 1; idx < 8; idx++) begin : GEN_loop fa fa0 (.a(a[idx]), .b(b[idx]), .cin(c[idx-1]), .s(s[idx]), .cout(c[idx])); end endgenerate assign s[8] = c[7];
ããã«å¯¾ãã¦ãFormalç¨ã®ã¢ãµã¼ã·ã§ã³ãå®è¡ããï¼
`ifdef FORMAL always_comb begin assert (s == {1'b0, a} + {1'b0, b}); end `endif // FORMAL
ããã«å¯¾ãã¦SymbiYosysãé©ç¨ããã以ä¸ãã¹ã¯ãªããï¼
[options] mode bmc depth 40 [engines] smtbmc z3 [script] read -sv -formal ha.v read -sv -formal fa.v read -sv -formal alu.v prep -top alu [files] ha.v fa.v alu.v
ãããå®è¡ããã¨ãSymbiYosysã¯ãã©ã¼ãã«æ¤è¨¼ãæåãããããã ã
$ sby -f alu_bmc.sby
SBY 1:03:08 [alu_bmc] engine_0: ## 0:00:00 Checking assumptions in step 39.. SBY 1:03:08 [alu_bmc] engine_0: ## 0:00:00 Checking assertions in step 39.. SBY 1:03:08 [alu_bmc] engine_0: ## 0:00:00 Status: passed SBY 1:03:08 [alu_bmc] engine_0: finished (returncode=0) SBY 1:03:08 [alu_bmc] engine_0: Status returned by engine: pass SBY 1:03:08 [alu_bmc] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0) SBY 1:03:08 [alu_bmc] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0) SBY 1:03:08 [alu_bmc] summary: engine_0 (smtbmc z3) returned pass SBY 1:03:08 [alu_bmc] summary: engine_0 did not produce any traces SBY 1:03:08 [alu_bmc] DONE (PASS, rc=0)