IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
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Updated
Nov 29, 2020 - VHDL
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
cryptography ip-cores in vhdl / verilog
Library of reusable VHDL components
Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA
My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.
This repository contains several VHDL codes of signal processing
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