…531)

- update opt_design_pre.tcl as recommended by Xilinx
- fixes an issue which incorrectly calculated timing paths
  using different point of origin for Source and Destination clock.
  For example a timing path using clk_main_a0 was computed using:
      Source Clock origin = WRAPPER_INST/CL/clk_main_a0
      Destination Clock origin = static_sh/pcie_inst/…*/TXOUTCLK
  This resulted in Hold Time Violations in certain customer designs.
- per Xilinx, this was happening because of adding SH_CL_BB_routed.dcp
  without closing post synthesis DCP.
- Update PYTHONPATH in the common env settings to fix vrs bug

* Update DCV.md (#697)

* Update and fix test failures (#698)
    * Fixed the non root test 
    * Fixed documentation link failures by adding an updated ssl context

* Update afi power doc (#699)
    * specify afi-power warning/violation triggers
    * Describe when afi-power-warning and afi-power-violation conditions trigger.
    * fix indentation of sh_cl_pwr_state

Co-authored-by: kyyalama2 <[email protected]>
Co-authored-by: AWScsaralay <[email protected]>

…pply changes seen in @jberaud's commit in Xilinx's dma_ip_drivers PR#69 (#536)

* Updated README.md and FAQ.md: (#702)

* Added descriptions on kernel clocks and frequency scaling.

* Virtual Ethernet upgrade (#694)

* Update dpdk to v20.02 for virtual eth instance and dpdk to v20.08 and pktgen to v20.09 for pktgen instance

* update to include a dpdk patch for generating igb

* update the script to also generate igb_uio.ko for x86_64-native-linuxapp-gcc

* updated dpdk patches for 20.02

* updates to spp_ethdev.c

* remove spp_ethdev.c as its updated in 0001 patch

* update the patch to enable igb_uio compilation

* updates to virtual_ethernet_install.py for upgrade to 20.02

* Update Virtual_Ethernet_Application_Guide.md

* Updated the end of life announcement table (#703)

Co-authored-by: czfpga <[email protected]>
Co-authored-by: kyyalama2 <[email protected]>