Fix IPI build script and Pythonpath bugs #535
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
- update opt_design_pre.tcl as recommended by Xilinx
- fixes an issue which incorrectly calculated timing paths
using different point of origin for Source and Destination clock.
For example a timing path using clk_main_a0 was computed using:
Source Clock origin = WRAPPER_INST/CL/clk_main_a0
Destination Clock origin = static_sh/pcie_inst/…*/TXOUTCLK
This resulted in Hold Time Violations in certain customer designs.
- per Xilinx, this was happening because of adding SH_CL_BB_routed.dcp
without closing post synthesis DCP.
- Update PYTHONPATH in the common env settings to fix vrs bug
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
using different point of origin for Source and Destination clock.
For example a timing path using clk_main_a0 was computed using:
Source Clock origin = WRAPPER_INST/CL/clk_main_a0
Destination Clock origin = static_sh/pcie_inst/…*/TXOUTCLK
This resulted in Hold Time Violations in certain customer designs.
without closing post synthesis DCP.
Issue #, if available:
Description of changes:
By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.