Fix IPI build script and Pythonpath bugs (#535)

- update opt_design_pre.tcl as recommended by Xilinx - fixes an issue which incorrectly calculated timing paths using different point of origin for Source and Destination clock. For example a timing path using clk_main_a0 was computed using: Source Clock origin = WRAPPER_INST/CL/clk_main_a0 Destination Clock origin = static_sh/pcie_inst/…*/TXOUTCLK This resulted in Hold Time Violations in certain customer designs. - per Xilinx, this was happening because of adding SH_CL_BB_routed.dcp without closing post synthesis DCP. - Update PYTHONPATH in the common env settings to fix vrs bug
aws · Sep 14, 2021 · a234375 · a234375
1 parent 90bf058
commit a234375
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Showing 2 changed files with 13 additions and 11 deletions.
diff --git a/hdk/common/shell_v04261818/hlx/build/scripts/subscripts/opt_design_pre.tcl b/hdk/common/shell_v04261818/hlx/build/scripts/subscripts/opt_design_pre.tcl
@@ -43,9 +43,8 @@ if {$_this_flow_option eq 1} {
 	#close the current design, read in both checkpoints, link & write, then continue with normal (subverted) flow
 	report_property [current_design]
 
-	add_files $::env(HDK_SHELL_DIR)/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
 
-	
+
 	set AWS_RTL_XDC_EXISTS [get_files */cl_synth_aws.xdc -quiet]
 
 	set BD_PATH_EXISTS [get_files */cl.bd -quiet]
@@ -58,9 +57,13 @@ if {$_this_flow_option eq 1} {
 		set BD_MODE ""
 		}
 	} else {
-		set BD_MODE ""	
+		set BD_MODE ""
 	}
-
+
+	close_design
+
+	add_files $::env(HDK_SHELL_DIR)/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
+
 	#RTL Flow or IPI Flow
 	if {$AWS_RTL_XDC_EXISTS != "" || $BD_MODE  == "None" } {
 	add_files $FAAS_CL_DIR/build/checkpoints/CL.post_synth_inline.dcp
@@ -69,13 +72,14 @@ if {$_this_flow_option eq 1} {
 	add_files $FAAS_CL_DIR/build/checkpoints/CL.post_synth.dcp
 	set_property SCOPED_TO_CELLS {WRAPPER_INST/CL} [get_files $FAAS_CL_DIR/build/checkpoints/CL.post_synth.dcp]
 	}
-
+
+
 	read_xdc $::env(HDK_SHELL_DIR)/build/constraints/cl_ddr.xdc
-	
+
 	set PNR_USR_LOC $::env(PNR_USER)
 	read_xdc ${PNR_USR_LOC}
 	set_property PROCESSING_ORDER LATE [get_files $PNR_USR_LOC]
-	set_property USED_IN {implementation} [get_files $PNR_USR_LOC]	
+	set_property USED_IN {implementation} [get_files $PNR_USR_LOC]
 
 	link_design -top $top -part [get_parts -of_objects [current_project]] -reconfig_partitions {WRAPPER_INST/SH WRAPPER_INST/CL}
 	source ${FAAS_CL_DIR}/build/constraints/aws_gen_clk_constraints.tcl
@@ -96,7 +100,7 @@ if {$_this_flow_option eq 1} {
 	}
 
 	source $::env(HDK_SHELL_DIR)/build/scripts/check_uram.tcl
-	
+
 	write_checkpoint -force $FAAS_CL_DIR/build/checkpoints/${timestamp}.SH_CL.post_link_design.dcp
 
 
@@ -106,5 +110,3 @@ if {$_this_flow_option eq 1} {
 	puts "NOT YET IMPLEMENTED!"
 	close design
 }
-
-
diff --git a/shared/bin/set_common_env_vars.sh b/shared/bin/set_common_env_vars.sh
@@ -68,8 +68,8 @@ export VITIS_DIR=$AWS_FPGA_REPO_DIR/Vitis
 # PYTHONPATH
 # Update PYTHONPATH with libraries used for unit testing
 python_lib=$AWS_FPGA_REPO_DIR/shared/lib
-export PYTHONPATH=$(echo $PATH | sed -e 's/\(^\|:\)[^:]\+$python_lib\(:\|$\)/:/g; s/^://; s/:$//')
 PYTHONPATH=$python_lib:$PYTHONPATH
+export PYTHONPATH
 
 # PATH Changes