staticvoid * __init memblock_alloc_internal(
phys_addr_t size, phys_addr_t align,
phys_addr_t min_addr, phys_addr_t max_addr,
int nid, bool exact_nid)
{
phys_addr_t alloc;
/* * Detect any accidental use of these APIs after slab is ready, as at * this moment memblock may be deinitialized already and its * internal data may be destroyed (after execution of memblock_free_all) */if (WARN_ON_ONCE(slab_is_available()))
returnkzalloc_node(size, GFP_NOWAIT, nid);
if (max_addr > memblock.current_limit)
max_addr = memblock.current_limit;
alloc = memblock_alloc_range_nid(size, align, min_addr, max_addr, nid,
exact_nid);
/* retry allocation without lower limit */if (!alloc && min_addr)
alloc = memblock_alloc_range_nid(size, align, 0, max_addr, nid,
exact_nid);
if (!alloc)
returnNULL;
returnphys_to_virt(alloc);
}
åãè¾¼ã¾ããããã»ã¹ãä¸æããã³ã³ããã¹ããä¿åã victim process ã«å¦çãæ»ãã¾ããåãè¾¼ã¾ããããã»ã¹ã¯ãã¤ã§ãåéã§ãã¾ãã
When the value of HCR_EL2.CD is 1:
â All stage 2 translations for data accesses to Normal memory are Non-cacheable.
â All accesses to the EL1&0 stage 2 translation tables are Non-cacheable.
⢠When the value of HCR_EL2.ID is 1:
â All stage 2 translations for instruction accesses to Normal memory are Non-cacheable.
CDã1ã«ããã¨ï¼
Stage 2å¤æãä»ãã¦ã¢ã¯ã»ã¹ããã Normal Memory ã¯å ¨ã¦ Non-cacheable ã«ãªãï¼