比做算法的懂工程落地，比做工程的懂算法模型。

Parametric layout generator for digital, analog and mixed-signal integrated circuits

Skywater 130nm Klayout Device Generators PDK

Conda + KLayout

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Carleton University / ELEC4609 - Integrated Circuit Design and Fabrication / Project: Static Logic PRSG (Pseudo Random Sequence Generator) chip design, fabrication and testing.

VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.

Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) architecture. Open NPU aims to democratize access to cutting-edge neural processing technology for machine learning and AI applications.