altera-fpga

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Here are 59 public repositories matching this topic...

drandyhaas / HaasoscopePro

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An Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

oscilloscope adc pyqtgraph altera-fpga

Updated Nov 25, 2024
Verilog

mbtaylor1982 / ReSDMAC

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Verilog code to replace the Commodore SDMAC found in the A3000

open-source amiga verilog kicad amiga-hardware altera-fpga

Updated Nov 24, 2024
Verilog

This project involves configuring a NIOS II softcore processor on the Altera DE10-Lite FPGA using Quartus Prime. It includes the creation of a custom Board Support Package (BSP), hardware abstraction layer (HAL), and drivers to optimize processor performance.

hal eclipse-ide embedded-c quartus altera-fpga nios-ii

Updated Nov 19, 2024
Verilog

Jjateen / Snake-Game-Verilog

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This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

fpga verilog quartus-prime de10-lite altera-fpga verilog-project

Updated Nov 4, 2024
Verilog

ThuyPham / FPGA-Toturial

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FPGA Tutorial Basic thuypx.com

fpga vivado testbench xilinx-fpga quartus altera-fpga fpga-programming

Updated Oct 27, 2024
VHDL

TanumaHideki / ReLM-PoC

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ReLM is the soft-core multiprocessor technology based on the unique memory architecture, enabling users to build a high-performance microcontroller on a relatively small FPGA board.

game python fpga multiprocessing parallel parallel-computing verilog altera parallel-processing multiprocessor softcore altera-fpga relm register-less bubble-estate

Updated Nov 24, 2024
Python

MUDAL / Altera_FPGA_Projects

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This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification

Updated Sep 11, 2024
C

LojananS / 305-team-21

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Team 21 - Mini-Project

vhdl flappy-bird vga quartus-prime altera-fpga de0-cv

Updated Jul 30, 2024
VHDL

Multimedia-Processing / Digital-Logic-Design

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透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Updated Oct 25, 2023
Verilog

HaochengBillYang / ece385

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ECE385 @ UIUC FA22

systemverilog altera-fpga uiuc-ece

Updated Oct 10, 2023
Verilog

mrLSD / fpga

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Research & Development FPGA projects for different boards

fpga verilog systemverilog altera-fpga sipeed-tang-nano-9k

Updated Oct 1, 2023
GLSL

gaikwadabhishek / flappy-bird-fpga-vhdl

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Flappy Bird on FPGA using VHDL

fpga vhdl flappy-bird altera-fpga fpga-programming cyclone-ii

Updated May 2, 2023
HTML

asankaSovis / Position_Detection

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📌 The idea of this project is to build a system that uses the existing lights to detect the location of a user within an indoor environment. For this, we can use Visible Light Communication (VLC) technology. The basic concept is to have four LEDs transmitting their IDs one after the other at fixed intervals.

c-sharp arduino fpga intel visible-light-communication uart-protocol serial-communication altera-fpga

Updated Apr 27, 2023
Verilog

william-hazem / LASD

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Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6

mips verilog altera-fpga