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altera-fpga

Here are 59 public repositories matching this topic...

ultraembedded / openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

fpga verilog logic-analyzer xilinx-fpga altera-fpga lattice-fpga digital-signal-analyzer ftdi232h ftdi2232h

Updated Jun 24, 2021
Verilog

HPS2FPGAmapping

robseb / HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

Updated Jun 9, 2021
Verilog

mbtaylor1982 / ReSDMAC

Verilog code to replace the Commodore SDMAC found in the A3000

open-source amiga verilog kicad amiga-hardware altera-fpga

Updated Nov 24, 2024
Verilog

drandyhaas / HaasoscopePro

An Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

oscilloscope adc pyqtgraph altera-fpga

Updated Nov 25, 2024
Verilog

Multimedia-Processing / Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Updated Oct 25, 2023
Verilog

alvarezpj / single-cycle-cpu

VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls

fpga vhdl quartus single-cycle de2-board altera-fpga

Updated Dec 17, 2019
VHDL

ThePituLegend / RISC-V_DE10-Nano

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

fpga riscv altera ucberkeley risc-v altera-fpga riscv-asm de10-nano riscv64 terasic rocketchip riscv-assembly chipyard

Updated Feb 7, 2022
Verilog

rafafigueredoviana / RISCV_MCU_CYCLONEV

A basic implementation of the RISCV core into a DE10nano FPGA board.

fpga riscv de10nano altera-fpga de10-nano pulpino

Updated Feb 19, 2020
SystemVerilog

atmughrabi / AccelGraph

Graph Processing Framework that supports || OpenMP || CAPI

Updated Jan 21, 2023
SystemVerilog

Davide-DD / mastermind

FPGA implementation of the popular logic game using VHDL and Altera DE1

fpga altera fpga-game mastermind vga fpga-board vga-controller altera-fpga vga-frame-buffer

Updated Apr 21, 2018
VHDL

mrLSD / fpga

Research & Development FPGA projects for different boards

fpga verilog systemverilog altera-fpga sipeed-tang-nano-9k

Updated Oct 1, 2023
GLSL

lazyoracle / vhdl-processor

An 8-bit processor in VHDL based on a simple instruction set

processor-architecture fpga processor vhdl verilog vivado hardware-designs hdl xilinx-fpga processor-simulator hardware-description-language digital-electronics altera-fpga processor-design

Updated Mar 7, 2019
VHDL

mateuspinto / FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

fpga verilog verilog-hdl fpga-firmware altera-fpga verilog-simulator verilog-project altera-de2

Updated Apr 25, 2019
Verilog

HaochengBillYang / ece385

ECE385 @ UIUC FA22

systemverilog altera-fpga uiuc-ece

Updated Oct 10, 2023
Verilog

MUDAL / Altera_FPGA_Projects

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification

Updated Sep 11, 2024
C

lstolcman / bachelor-thesis

Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract

fpga hardware signal-processing verilog sdr altera digital-signal-processing digital-design dcf77 dcf-decoder altera-fpga

Updated May 22, 2018
Verilog

Terminatorjjjjj / NTUEE-DCLAB-Materials

This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).

Updated Oct 26, 2019
SystemVerilog

XAli-SHX / Implementation-of-an-Edge-Detection-Filter-Using-the-Avalon-Interface

Implementation of an Edge Detection Filter Using the Avalon Interface

fpga verilog edge-detection avalon sobel quartus altera-fpga sobel-filter rgb2gray sobel-edge-detector avalon-bus avalon-streaming

Updated Jan 30, 2023
Verilog

mohamedtareq24 / 4_Channel_Logic_Analyzer

FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA

fpga verilog logic-analyzer quartus-prime altera-fpga

Updated Nov 21, 2022
Verilog

nikolovjovan / FPGAParallelSorting

Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.

vhdl altera altera-fpga terasic-de0 cyclone-iii

Updated Nov 14, 2020
VHDL

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