Unit 5

Sequential Circuit Description

1
Sequential Models

 In digital circuits, storage of data is done either by feedback, or by gate

capacitances that are refreshed frequently.

2
Sequential Models

Sequential
Models

Feedback Capacitive Implicit

Model Model Model

Verilog Digital 3
System Design
Feedback Model

Sequential
Models

Feedback Capacitive Implicit

Model Model Model

Verilog Digital 4
System Design
Feedback Model

A two-state (one-bit)
Memory element

S
Q
R

Feedback Line
 Basic Feedback

Verilog Digital 5
System Design
Capacitive Model

Sequential
Models

Feedback Capacitive Implicit

Model Model Model

Verilog Digital 6
System Design
Capacitive Model
When c becomes 1 the value of D
is saved in the input gate of the
inverter and when c becomes 0
this value will be saved until the
next time that c becomes 1 again.

C The complement
of the stored data

D Q

 Capacitive Storage

Verilog Digital 7
System Design
Implicit Model

Sequential
Models

Feedback Capacitive Implicit

Model Model Model

Verilog Digital 8
System Design
Implicit Model
Feedback and capacitive models Verilog offers language constructs
are technology dependent and that are technology independent
have the problem of being too and allow much more efficient
detailed and too slow to simulate. simulation of circuits with a large
number of storage elements.

1S Q

1R
C1
 An SR-Latch Notation

Verilog Digital 9
System Design
Basic Memory Components

Basic Memory
Components

User Defined
Gate Level Primitives
Sequential Primitives

Memory Elements Behavioral

Using Assignments Memory Elements

Memory Vectors
Flip-flop Timing
and Arrays

Verilog Digital 10
System Design
Gate Level Primitives

Basic Memory
Components

User Defined
Gate Level Primitives
Sequential Primitives

Memory Elements Behavioral

Using Assignments Memory Elements

Memory Vectors
Flip-flop Timing
and Arrays

Verilog Digital 11
System Design
Gate Level Primitives

latch 1-bit Storage

Element
s q_b
g1

r g2
q

 Cross-Coupled NOR Latch

Verilog Digital 12
System Design
Gate Level Primitives

Base of most static

memory components
`timescale 1ns/100ps

module latch (input s, r, output q, q_b );

nor #(4)
g1 ( q_b, s, q ), q and q_b outputs are
initially X and remain
g2 ( q, r, q_b );
at this ambiguous state
endmodule for as long as s and r
remain 0.
 SR-Latch Verilog Code
Simultaneous assertion
of both inputs results in
loss of memory.
Verilog Digital 13
System Design
Gate Level Primitives
Control Gates

Clock Input latch_p

s _s
g1 q
g3

g4
r g2 q_b
_r

 All NAND Clocked SR-Latch

Verilog Digital 14
System Design
Gate Level Primitives
Delay values can be
controlled when the latch
`timescale 1ns/100ps is instantiated.

module latch_p #(parameter tplh=3, tphl=5)

(input s, r, c, output q, q_b );
wire _s, _r; Set and Reset inputs to the
cross_coupled core of this
nand #(tplh,tphl) memory element

g1 ( _s, s, c ),
g2 ( _r, r, c ),
g3 ( q, _s, q_b ),
g4 ( q_b, _r, q );
endmodule

 All NAND Clocked Latch

Verilog Digital 15
System Design
Gate Level Primitives

 SR Latch Simulation This delay is due to a fall of

3ns and a rise of 5 ns in the
NAND gates of the circuit.

Verilog Digital 16
System Design
Gate Level Primitives

Master Slave
master_slave
d
latch qm latch q
c
~c q_b
~d qm_b

 Master-Slave D Flip-Flop

Verilog Digital 17
System Design
Gate Level Primitives

`timescale 1ns/100ps
module master_slave (input d, c, output q, q_b );
wire qm, qm_b;
defparam master.tplh=4, master.tphl=4,
Hierarchical Naming
slave.tplh=4, slave.tphl=4;

latch_p
master ( d, ~d, c, qm, qm_b ),
slave ( qm, qm_b, ~c, q, q_b );
endmodule

 Master-Slave D Flip-Flop Verilog Code

Verilog Digital 18
System Design
User Defined
Sequential Primitives
Basic Memory
Components
User Defined
Gate Level Primitives
Sequential Primitives

Memory Elements Behavioral

Using Assignments Memory Elements

Memory Vectors
Flip-flop Timing
and Arrays
Verilog Digital 19
System Design
User Defined
Sequential Primitives

 Verilog provides language constructs for defining sequential UDPs:

 Faster Simulation of memory elements
 Correspondence to specific component libraries

Verilog Digital 20
System Design
User Defined Sequential Primitives
primitive latch( q, s, r, c );
output q;
reg q;
input s, r, c;
initial q=1'b0;
table
// s r c q q+ ;
// ------:---:----;
? ? 0 : ? : - ; Table defining the latch
0 0 1 : ? : - ; output
0 1 1 : ? : 0 ;
1 0 1 : ? : 1 ;
endtable
endprimitive

 Sequential UDP Defining a Latch

Verilog Digital 21
System Design
User Defined Sequential Primitives
primitive latch( q, s, r, c );
.............
Column for specifying
............. present state
table
// s r c q q+ ;
Signifies “no change”
// ------:---:----;
? ? 0 : ? : - ;
0 0 1 : ? : - ;
0 1 1 : ? : 0 ;
1 0 1 : ? : 1 ; Signifies “any value”
endtable
endprimitive
 Sequential UDP Defining a Latch
Verilog Digital 22
System Design
Memory Elements Using
Assignments
Basic Memory
Components

User Defined
Gate Level Primitives
Sequential Primitives
Memory Elements
Memory Elements Behavioral
Using Assignments Memory Elements

Memory Vectors
Flip-flop Timing
and Arrays

Verilog Digital 23
System Design
Memory Elements Using
When a block’s
clock input is 0,
Assignments
it puts its output master_slave
back
to itself (feedback),
and when its clock is
1 it puts its data
input
into its output. d qm q

c
~c

 Master-Slave Using Two Feedback Blocks

Verilog Digital 24
System Design
Memory Elements Using
Assignments
`timescale 1ns/100ps

module master_slave_p #(parameter delay=3)

(input d, c, output q);
wire qm; The feedback of qm
output back to its input
assign #(delay) qm = c ? d : qm;
assign #(delay) q = ~c ? qm : q;
Each assign statement
endmodule implements a latch
Complementary Clocks:
Implements
 Assign Statements Implementing Logicmaster-slave
Feedback
flip-flop

Verilog Digital 25
System Design
Behavioral Memory Elements

Basic Memory
Components

User Defined
Gate Level Primitives
Sequential Primitives

Memory Elements Behavioral

Behavioral
Using Assignments Memory
Memory Elements
Elements
Memory Vectors
Flip-flop Timing
and Arrays

Verilog Digital 26
System Design
Behavioral Memory Elements

 Behavioral Coding:
 A more abstract and easier way of writing Verilog code for a latch or
flip-flop.
 The storage of data and its sensitivity to its clock and other control
inputs will be implied in the way model is written.

Verilog Digital 27
System Design
Behavioral Memory Elements
Behavioral
Memory
Elements

Latch Flip-flop
Modeling Modeling

Flip-flop Other
with Set-Reset Storage Element
Control Modeling Styles
Verilog Digital 28
System Design
Latch Modeling
Behavioral
Memory
Elements

Latch
Latch Flip-flop
Modeling
Modeling Modeling

Flip-flop Other
with Set-Reset Storage Element
Control Modeling Styles
Verilog Digital 29
System Design
While c is 1
Latch Modeling
changes on d directly affect
q and q_b outputs.
A Storage unit
Level Sensitive to c :
`timescale 1ns/100ps A Latch

module latch (input d, c, output reg q, q_b );

always @( c or d )
if ( c )
begin After 4ns d input is read
#4 q = d; and assigned to q output.
#3 q_b = ~d; If d changes between the
end time it is read for q and q_b
endmodule erroneous results happen.

 A D-Type Latch Verilog Code After another wait of 3ns, d

is read again and ~d is
assigned to q_b output.
Verilog Digital 30
System Design
Latch Modeling
Corrects the timing
problem of blocking
`timescale 1ns/100ps assignments.

module latch (input d, c, output reg q, q_b );

always @( c or d )
if ( c )
begin
q <= #4 d;
q_b <= #3 ~d;
end
endmodule
Non-blocking assignments
 Latch Model Using Nonblocking Assignments With intra-statement delay
controls
Verilog Digital 31
System Design
Latch Modeling

 Testing Latch with Nonblocking Assignments

Storing a 0
at time 50
Storing a 1
at time 30
Verilog Digital 32
System Design
Flip-flop Modeling
Behavioral
Memory
Elements

Latch Flip-flop
Flip-flop
Modeling Modeling
Modeling

Flip-flop Other
with Set-Reset Storage Element
Control Modeling Styles
Verilog Digital 33
System Design
Flip-flop Modeling
With each clock edge,
the entire procedural block
is executed once from begin A basic edge trigger
to end. flip-flop model at the
behavioral level
`timescale 1ns/100ps

module d_ff (input d, clk, output reg q, q_b );

always @( posedge clk )
Sensitive to the
begin positive edge of the clock
q <= #4 d;
Assignments to q and q_b
q_b <= #3 ~d; are reached immediately
end after the flow in always block
endmodule begins.

 Positive Edge Trigger Flip-Flop

The actual assignments of
values are delayed.
Verilog Digital 34
System Design
Flip-flop Modeling
During the time clk is 1 (from 60ns
to 80ns exclusive of 60 and
inclusive of 80), changes on d do
not affect the state of flip-flop

At 60ns, on the positive edge of

 Simulation of a Positive Edge Flip-Flop
clock, the value of d is read and
scheduled into q and q_b for times
64ns and 63ns respectively.

Verilog Digital 35
System Design
Flip-flop with Set-Reset Control
Behavioral
Memory
Elements

Latch Flip-flop
Modeling Modeling

Flip-flop
Flip-flop Other
with Set-Reset
with Set-Reset Storage Element
Control
Control Modeling Styles
Verilog Digital 36
System Design
Flip-flop With Set-Reset Control
`timescale 1ns/100ps

module d_ff_sr_Synch (input d, s, r, clk, output reg q, q_b );

always @(posedge clk) begin
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule

 D Type Flip-Flop with Synchronous Control

Verilog Digital 37
System Design
Flip-flop With Set-Reset Control
module d_ff_sr_Synch (input d, s, r, clk,
output reg q, q_b );
always @(posedge clk) begin
The flow into always block
if( s ) begin is only initiated by the
................. posedge of clk
end else if( r ) begin
................. These if-statements with
end else begin s and r conditions are only
examined after the positive
.................
edge of the clock
end
end Synchronous s and r control inputs
endmodule
 D Type Flip-Flop with Synchronous Control (Continued)
Verilog Digital 38
System Design
Flip-flop With Set-Reset Control
..................
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1; These if-statements with
s and r conditions are only
end else begin examined after the positive
q <= #4 d; edge of the clock
q_b <= #3 ~d;
end
..................
 D Type Flip-Flop with Synchronous Control (Continued)
Verilog Digital 39
System Design
Flip-flop With Set-Reset Control
`timescale 1ns/100ps
module d_ff_sr_Asynch (input d, s, r, clk, output reg q, q_b );
always @( posedge clk, posedge s, posedge r )
begin
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule

 D-type Flip-Flop with Asynchronous Control

Verilog Digital 40
System Design
Flip-flop With Set-Reset Control
module d_ff_sr_Asynch (input d, s, r, clk,
output reg q, q_b );
always @( posedge clk, posedge s, posedge r ) begin
if( s ) begin
The sensitivity list of the
.................... always block
end else if( r ) begin
.................... Asynchronous
end else begin set and reset inputs
....................
end
end
endmodule
 D-type Flip-Flop with Asynchronous Control (Continued)
Verilog Digital 41
System Design
Flip-flop With Set-Reset Control
....................
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
This flip-flop is sensitive to
q <= #4 1'b0;
the edge of clock, but to the
q_b <= #3 1'b1; levels of s and r .
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
....................
 D-type Flip-Flop with Asynchronous Control (Continued)
Verilog Digital 42
System Design
Flip-flop With Set-Reset Control
Before 120 ns, changes to q is
s and r become active and
triggered by the clock and
cause changes to the flip-flop
q_Synch and q_Asynch are the
output.
same.

 Comparing Synchronous and Asynchronous q_Asynch

Flip-Flopchanges occur
Controls
independent of the clock when
q_Synch will waits for the edge s or r becomes active
of the clock to set or reset
Verilog Digital 43
System Design
Other Storage Element Modeling Styles
Behavioral
Memory
Elements

Latch Flip-flop
Modeling Modeling

Flip-flop Other
Other Storage
with Set-Reset Element Modeling
Storage Element
Control StyleStyles
Modeling
Verilog Digital 44
System Design
Other Storage Element
Modeling Styles A latch using a wait
statement instead of an
`timescale 1ns/100ps event control statement

module latch (input d, c, output reg q, q_b );

Blocks the flow of procedural
always begin block when c is 0.
wait ( c ); If c becomes 1 and remains at
#4 q <= d; this value, the body of the
#3 q_b <= ~d; always statement repeats itself
every 7 ns.
end
endmodule If the delay control statements
are omitted, then the looping of
 Latch Using wait, a Potentially Dangerous
the always Model
block happens in zero
time, causing an infinite loop in
Verilog Digital simulation.
45
System Design
Flip-flop Timing

Basic Memory
Components

User Defined
Gate Level Primitives
Sequential Primitives

Memory Elements Behavioral

Using Assignments Memory Elements

Memory Vectors
Flip-flop
Flip-flop Timing
Timing
and Arrays

Verilog Digital 46
System Design
Flip-flop Timing

Flip-flop
Timing

Width
Setup Hold
And
Time Time
Period

Verilog Digital 47
System Design
Setup Time

Flip-flop
Timing

Width
Setup Hold
And
Time Time
Period

Verilog Digital 48
System Design
Setup Time

 Setup Time
 The Minimum necessary time that a data input requires to setup
before it is clocked into a flip-flop.
 Verilog construct for checking the setup time: $setup task
 The $setup task:
 Takes flip-flop data input, active clock edge and the setup time as
its parameters.
 Is used within a specify block.

Verilog Digital 49
System Design
Setup Time Continuously checks timing
distance between changes on d
$setup task within a specify block and the positive edge of clk.
If this distance is less than 5ns,
`timescale 1ns/100ps a violation message will be issued.
module d_ff ( input d, clk, s, r, output reg q, q_b
);
specify
$setup ( d, posedge clk, 5 );
endspecify
always @( posedge clk or posedge s or posedge r )
begin
.............. Positive edge trigger flip-flop
end and Asynchronous set and
reset controls
endmodule
 Flip-Flop with Setup Time

Verilog Digital 50
System Design
Setup Time
...................................
always @( posedge clk or posedge s or posedge r )
begin
if( s ) begin
q <= #4 1'b1;
q_b <= #3 1'b0;
end else if( r ) begin
q <= #4 1'b0;
q_b <= #3 1'b1;
end else begin
q <= #4 d;
q_b <= #3 ~d;
end
end
endmodule

 Flip-Flop with Setup Time (Continued)

Verilog Digital 51
System Design
Setup TimeThe d input changes at 57ns
and the data is clocked into
the flip-flop at 60ns,
only 3ns after d.

 Setup Time Violation The simulation run reports

the violation.

Verilog Digital 52
System Design
Hold Time

Flip-flop
Timing

Width
Setup Hold
And
Time Time
Period

Verilog Digital 53
System Design
Hold Time

 Hold Time
 The Minimum necessary time a flip-flop data input must stay
stable (holds its value) after it is clocked.
 Verilog construct for checking the setup time: $hold task
 The $setup task:
 Takes flip-flop data input, active clock edge and the required hold
time as its parameters.
 Is used within a specify block.

Verilog Digital 54
System Design
Hold Time
`timescale 1ns/100ps

module d_ff ( input d, clk, s,Flip-flop with holdreg

r, output time q,
of 3ns.
q_b);
specify
$hold ( posedge clk, d, 3 );
endspecify
always @( posedge clk or posedge s or posedge r )
begin
..............................................
end
endmodule

 Flip-Flop with Hold Time

Verilog Digital 55
System Design
Hold Time
The clock samples the d value
of 1 at 20ns. At 22ns, d changes.
This violates the minimum
required hold time of 3ns.

 Hold Time Violation

Verilog Digital 56
System Design
Hold Time

 The Verilog $setuphold task combines setup and hold timing checks.
 Example:
 $setuphold (posedge clk, d, 5, 3)

Verilog Digital 57
System Design
Width And Period

Flip-flop
Timing

Width
Setup Hold
And
Time Time
Period

Verilog Digital 58
System Design
Width And Period

 Verilog $width and $period check for minimum pulse width and period.

 Pulse Width: Checks the time from a specified edge of a reference

signal to its opposite edge.

 Period: Checks the time from a specified edge of a reference signal to

the same edge.

Verilog Digital 59
System Design
Width And Period
specify
$setuphold ( posedge clk, d, 5, 3 );
$width (posedge r, 4);
$width (posedge s, 4);
$period (negedge clk, 43);
endspecify

always @( posedge clk or posedge s or posedge r )

if( s ) q <= #4 1'b1;
else if( r ) q <= #4 1'b0;
else q <= #4 d;
................................

 Setup, Hold, Width, and Period Checks (Continued)

Verilog Digital 60
System Design
Controllers

Component
Description

Data
Controllers
Controllers
Components

Verilog Digital 61
System Design
Controllers

Decisions
Based on :Inputs ,
Outputs ,State

Issue Control Signal

Set Next State

Go to Next State
 Controller Outline

Verilog Digital 62
System Design
Controllers

 Controller:
 Is wired into data part to control its flow of data.

 The inputs to controller determine its next states and outputs.

 Monitors its inputs and makes decisions as to when and what output
signals to assert.
 Keeps the history of circuit data by switching to appropriate states.

 Two examples to illustrate the features of Verilog for describing state

machines:
 Synchronizer

 Sequence Detector

Verilog Digital 63
System Design
Controllers

Controllers

Sequence
Synchronizer
Detector

Verilog Digital 64
System Design
Synchronizer

Controllers

Sequence
Synchronizer
Synthesizer
Detector

Verilog Digital 65
System Design
Synchronizer

Clk

adata

synched

 Synchronizing adata

Verilog Digital 66
System Design
Synchronizer

`timescale 1ns/100ps

module Synchronizer (input clk, adata,

output reg synched);
always @(posedge clk)
if (adata == 0) synched <= 0; If a 1 is Detected on
else synched <= 1; adata on the rising
endmodule edge of clock,
synched becomes 1
 A Simple Synchronization Circuit and remains 1
for at least one
clock period

Verilog Digital 67
System Design
Sequence Detector

Controllers

Sequence
Sequence
Synthesizer
Detector
Detector

Verilog Digital 68
System Design
Sequence Detector
When the sequence
Searches on is detected, the w
it’s a input Output becomes 1
for the and stays 1 for a
110 Sequence complete clock cycle
If 110 is detected
a on a, then w gets w
1, else w gets 0.

clk
 State Machine Description

Verilog Digital 69
System Design
Sequence Detector
A Moore Machine
Sequence Detector
States are named: The State in which
s0 , s1 , s2 , s3 the 110 sequence is
detected.
0 1
reset
1 1 0
S0 S1 S2 S3
0 0 0 0 1
1
Initia
l 0
State
It Takes at least
3 clock periods to
get to the s3 state
 Sequence Detector State Machine

Verilog Digital 70
System Design
Sequence Detector
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
reg [1:0] current;

always @(posedge clk) begin

if (reset) current = s0;
else
case (current)
s0: if (a) current <= s1; else current <= s0;
s1: if (a) current <= s2; else current <= s0;
s2: if (a) current <= s2; else current <= s3;
s3: if (a) current <= s1; else current <= s0;
endcase
end

assign w = (current == s3) ? 1 : 0;

endmodule

 Verilog Code for 110 Detector

Verilog Digital 71
System Design
State Machine Coding

State Machine
Coding

Moore Machines Mealy Machines

Huffman A More Modular

Coding Style Style

A ROM Based
Controller

Verilog Digital 72
System Design
Moore Machines

State Machine
Coding

Moore Machines Mealy Machines

Huffman A More Modular

Coding Style Style

A ROM Based
Controller

Verilog Digital 73
System Design
Moore Machines

 Moore Machine :
 A state machine in which all outputs are carefully synchronized
with the circuit clock.
 In the state diagram form, each state of the machine specifies its
outputs independent of circuit inputs.
 In Verilog code of a state machine, only circuit state variables
participate in the output expression of the circuit.

Verilog Digital 74
System Design
Mealy Machines

State Machine
Coding

Moore Machines Mealy Machines

Huffman A More Modular

Coding Style Style

A ROM Based
Controller

Verilog Digital 75
System Design
Mealy Machines

 Mealy Machine :
 Is different from a Moore machine in that its output depends on its
current state and inputs while in that state.
 State transitions and clocking and resetting the machine are no
different from those of a Moore machine. The same coding
techniques are used.

Verilog Digital 76
System Design